Abstract: In some embodiments, the present disclosure relates to a device that includes an active layer, a gate electrode, a passivation structure, a source contact, and a drain contact arranged over a substrate. The gate electrode is arranged over the substrate and is spaced apart from the active layer by a gate dielectric layer. The passivation structure is arranged over the active layer. The source contact extends through the passivation structure and contacts the active layer. The drain contact extends through the passivation structure and contacts the active layer. The passivation structure is hydrophobic.

Abstract: An apparatus (e.g., a user equipment (UE)) maps a plurality of mutually orthogonal sequences to each of a plurality of physical resource blocks (PRBs) within an interlace. The apparatus then performs a physical uplink control channel (PUCCH) transmission in a New Radio unlicensed spectrum (NR-U). The apparatus also receives an assignment of a set of sequences for each PRB of the plurality of PRBs from a wireless network. In response, the apparatus performs an uplink control information (UCI) transmission via the PUCCH in the NR-U.

Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench; depositing a first metal oxide layer over the interfacial layer; removing the first metal oxide layer from the pFET structure; depositing a ferroelectric layer in each gate trench; depositing a second metal oxide layer over the ferroelectric layer; removing the second metal oxide layer from the nFET structure; and depositing a gate electrode in each gate trench.

Abstract: Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.

Abstract: An electroluminescent device, wherein the electroluminescent device includes a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, an active layer, a first electrode, a second electrode, and an optical conversion material. The active layer is disposed between the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer and electrically connected with these two. The first-conductivity-type semiconductor layer has a light-emitting surface disposed on a side opposite to the active layer, and includes a plurality of 3D structures arranged regularly, extending from the light-emitting surface towards the active layer to jointly define at least one cavity having a depth greater than 70% a thickness of the first-conductivity-type semiconductor layer. The optical conversion material is filled in the cavity.

Abstract: The present invention relates to a structure of photodiode, which comprises a substrate, a first electrode, an electron transport layer, a photoactive layer, a filter layer, and a second electrode. The first electrode is disposed on the substrate. The electron transport layer is disposed on the first electrode. The photoactive layer is disposed on the electron transport layer. The photoactive layer has a first energy gap value. The filter layer is disposed on the photoactive layer and has a second energy gap value. The second electrode is disposed on the filter layer. The second energy gap value is greater than the first energy gap value. The ratio of the second energy gap value to the first energy gap value is an energy gap ratio. The energy gap ratio is greater than 1 and less than or equal to 3.

Abstract: A light source device includes a substrate, a light emitting unit, a frame, a light permeable member, and a metal shield. An upper electrode layer and a lower electrode layer of the substrate are respectively disposed on two opposite sides of the substrate, and are electrically coupled to each other. The light emitting unit is disposed on the upper electrode layer. The frame is disposed on the substrate and is arranged around the light emitting unit. The light permeable member is disposed on the frame and covers the light emitting unit. The metal shield is fixed to an inner side of the frame and is connected to the ground pad of the upper electrode layer. The metal shield is arranged around the outer side of the light emitting unit.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain layer surrounding the first nanostructure and adjacent to the gate stack. The semiconductor device structure includes a contact structure surrounding the first source/drain layer, wherein a first portion of the contact structure is between the first source/drain layer and the substrate.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a dielectric layer disposed over a portion of the substrate. The semiconductor device includes a diffusion blocking layer disposed over the dielectric layer. The diffusion blocking layer and the dielectric layer have different material compositions. The semiconductor device includes a ferroelectric layer disposed over the diffusion blocking layer.

Abstract: An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The IC structure includes a front end of line (FEOL) device layer having a plurality of active devices, a first back end of line (BEOL) interconnect structure on the (FEOL) device layer, and a nanowire switch on the first BEOL interconnect structure. A first end of the nanowire switch is connected to an active device of the plurality of active devices through the first BEOL interconnect structure. The IC structure further includes a second BEOL interconnect structure on the nanowire switch. A second end of the nanowire switch is connected to a power source through the second BEOL interconnect structure and the second end is opposite to the first end.

Abstract: The disclosure provides a mixed rendering system and a mixed rendering method. The mixed rendering system includes a client device configured to perform: determining at least one user-interactable object of a virtual environment; rendering the at least one user-interactable object; receiving a background scene frame of the virtual environment; blending the at least one rendered user-interactable object with the background scene frame as a visual content of the virtual environment; and providing the visual content of the virtual environment.

Abstract: An integrated circuit device includes a first-type active-region semiconductor structure, a first gate-conductor, a second-type active-region semiconductor structure that is stacked with the first-type active-region semiconductor structure, and a second gate-conductor. The integrated circuit device also includes a front-side conductive layer above the two active-region semiconductor structures and a back-side conductive layer below the two active-region semiconductor structures. The integrated circuit device also includes a front-side power rail and a front-side signal line in the front-side conductive layer and includes a back-side power rail and a back-side signal line in the back-side conductive layer. The integrated circuit device also includes a first source conductive segment connected to the front-side power rail and a second source conductive segment connected to the back-side power rail.

Abstract: A disclosed transistor structure includes a gate electrode, an active layer, a source electrode, a drain electrode, an insulating layer separating the gate electrode from the active layer, and a carrier modification device that reduces short channel effects by reducing carrier concentration variations in the active layer. The carrier modification device may include a capping layer in contact with the active layer that acts to increase a carrier concentration in the active layer. Alternatively, the carrier modification device may include a first injection layer in contact with the source electrode and the active layer separating the source electrode from the active layer, and a second injection layer in contact with the drain electrode and the active layer separating the drain electrode from the active layer. The first and second injection layers may act to reduce a carrier concentration within the active layer near the source electrode and the drain electrode.

Abstract: A semiconductor device with air spacers and air caps and a method of fabricating the same are disclosed. The semiconductor device includes a substrate and a fin structure disposed on the substrate. The fin structure includes a first fin portion and a second fin portion. The semiconductor device further includes a source/drain (S/D) region disposed on the first fin portion, a contact structure disposed on the S/D region, a gate structure disposed on the second fin portion, an air spacer disposed between a sidewall of the gate structure and the contact structure, a cap seal disposed on the gate structure, and an air cap disposed between a top surface of the gate structure and the cap seal.

Abstract: Semiconductor devices including backside capacitors and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including a front-side conductive line; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a backside conductive line, the backside conductive line having a line width greater than a line width of the front-side conductive line; and a first capacitor structure coupled to the backside interconnect structure.

Abstract: The present disclosure is directed to methods for the formation of high-voltage nano-sheet transistors and low-voltage gate-all-around transistors on a common substrate. The method includes forming a fin structure with first and second nano-sheet layers on the substrate. The method also includes forming a gate structure having a first dielectric and a first gate electrode on the fin structure and removing portions of the fin structure not covered by the gate structure. The method further includes partially etching exposed surfaces of the first nano-sheet layers to form recessed portions of the first nano-sheet layers in the fin structure and forming a spacer structure on the recessed portions. In addition, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure abutting the fin structure.

Abstract: Semiconductor devices and methods are provided which facilitate performing physical failure analysis (PFA) testing from a backside of the devices. In at least one example, a device is provided that includes a semiconductor device layer including a plurality of diffusion regions. A first interconnection structure is disposed on a first side of the semiconductor device layer, and the first interconnection structure includes at least one electrical contact. A second interconnection structure is disposed on a second side of the semiconductor device layer, and the second interconnection structure includes a plurality of backside power rails. Each of the backside power rails at least partially overlaps a respective diffusion region of the plurality of diffusion regions and defines openings which expose portions of the respective diffusion region at the second side of the semiconductor device layer.

Abstract: A development system and a method of an offline software-in-the-loop simulation are disclosed. A common firmware architecture generates a chip control program. The common firmware architecture has an application layer and a hardware abstraction layer. The application layer has a configuration header file and a product program. A processing program required by a peripheral module is added to the hardware abstraction layer during compiling. The chip control program is provided to a controller chip or a circuit simulation software to be executed to control the product-related circuit through controlling the peripheral module.

Abstract: A method for UE capability signaling to support enhancements on resource allocation for Physical Downlink Control Channel (PDCCH) candidate monitoring in NR-U is proposed. A UE transfers UE capability information to a mobile communication network. The UE capability information includes information indicating whether the UE supports Control Resource Set (CORESET) configuration with a Resource Block (RB) offset. The UE receives resource allocation configuration of an unlicensed cell from the mobile communication network. The UE monitors PDCCH candidates on the unlicensed cell according to the resource allocation configuration.

Abstract: An apparatus (e.g., a user equipment (UE)) maps a plurality of mutually orthogonal sequences to each of a plurality of physical resource blocks (PRBs) within an interlace. The apparatus then performs a physical uplink control channel (PUCCH) transmission in a New Radio unlicensed spectrum (NR-U). The apparatus also receives an assignment of a set of sequences for each PRB of the plurality of PRBs from a wireless network. In response, the apparatus performs an uplink control information (UCI) transmission via the PUCCH in the NR-U.