Abstract: A current limiter and a charge pump regulator including the current limiter are provided. The charge pump regulator converts an input voltage to an output voltage and includes a feedback loop including a first transistor for regulating a discharge current from the charge pump regulator. The current limiter limits the current provided by the charge pump regulator. The current limiter includes a sampling block configured to sample a first drain-source voltage of the first transistor and hold it as a reference drain-source voltage; an adaptive tracking block configured to receive the reference drain-source voltage, and to generate a maximum voltage based on the reference drain-source voltage, so that the maximum voltage tracks the reference drain-source voltage; and a voltage clamp block configured to clamp a feedback voltage to the maximum voltage, and to provide the clamped voltage as a first gate-source voltage of the first transistor.

Abstract: Embodiments relate to a semiconductor structure and a method for fabricating the same. The semiconductor structure includes: a base substrate including a trench, where the trench includes a gate structure whose top surface is lower than a top surface of the trench; first etch stop layers, where the first etch stop layers cover the top surface of the gate structure, part of a side wall of the trench, and an upper surface of the base substrate; an enclosed isolation structure positioned between the first etch stop layers in the trench, where the enclosed isolation structure at least plugs an opening of the trench; and an air gap positioned between the first etch stop layer and the enclosed isolation structure, where the air gap at least includes a transverse portion, and a bottom of the enclosed isolation structure is positioned on the transverse portion.

Abstract: Embodiments of this application provide an LTCC microwave passive device. The LTCC microwave passive device includes a housing and a filter assembly. The housing includes a top portion, a bottom portion, and a side portion. The filter assembly is accommodated in the housing, and the filter assembly includes a first layer, a second layer, and a third layer. The first layer, the second layer, and the third layer are spaced apart sequentially in a direction from the top portion to the bottom portion, the first layer and the third layer are located on two opposite sides of the second layer respectively, the first layer includes at least two resonance units, each resonance unit includes a microstrip, the second layer includes a transfer busbar, and the microstrip of the resonance unit is connected to the transfer busbar through a corresponding first connection column and is grounded through the transfer busbar.

Abstract: A method for forming the active area includes the following operations. A semiconductor substrate is provided. A first mask layer and a second mask layer are sequentially formed on a surface of the semiconductor substrate, in which the second mask layer has an initial pattern for forming the active area. A sacrificial layer covering the second mask layer is formed. The sacrificial layer and a portion of the second mask layer are removed to form a third mask layer with a preset thickness, in which the preset thickness is less than an initial thickness of the second mask layer. The active area is formed through the third mask layer and the first mask layer.

Abstract: Provided is a segmented bending section assembly for a disposable ureteroscope, including a bending sectional tube, elastic tubes, and traction cables. Multiple U-shaped limiting grooves arranged in an axial direction of the bending sectional tube are formed in a side wall of a tail portion of the bending sectional tube. An end portion of each of the elastic tubes abuts against a bottom wall of each U-shaped limiting groove, a side wall of the elastic tube abuts against an inside wall of the U-shaped limiting groove, and the elastic tube is welded to the U-shaped limiting groove. A tube body of the bending sectional tube is internally provided with multiple wire-passing channels for the traction cables to pass through, and the traction cable penetrates through the elastic tube and the wire-passing channel and then are fixedly connected to a front end of the bending sectional tube.

Abstract: A test strip comprising a porous matrix, the test strip includes a sample application zone for applying a liquid sample including an analyte; a reporter release zone, having a sensing material, the sensing material being adapted to selectively interact with the analyte by releasing an optical reporter, the reporter release zone being arranged downstream of the sample application zone; and a detection zone, having a capture material, the capture material being adapted to selectively bind the optical reporter and being arranged downstream of the reporter release zone.

Abstract: Embodiments of the present application disclose a semiconductor structure, a formation method thereof and a memory. The semiconductor structure includes: a substrate; a channel located in the substrate, the channel being configured to form a gate structure; and a convex portion arranged on an inner wall of the channel. The embodiments of the present application can increase a channel length and solve a short-channel effect.

Abstract: A current limiter and a charge pump regulator including the current limiter are provided. The charge pump regulator converts an input voltage to an output voltage and includes a feedback loop including a first transistor for regulating a discharge current from the charge pump regulator. The current limiter limits the current provided by the charge pump regulator. The current limiter includes a sampling block configured to sample a first drain-source voltage of the first transistor and hold it as a reference drain-source voltage; an adaptive tracking block configured to receive the reference drain-source voltage, and to generate a maximum voltage based on the reference drain-source voltage, so that the maximum voltage tracks the reference drain-source voltage; and a voltage clamp block configured to clamp a feedback voltage to the maximum voltage, and to provide the clamped voltage as a first gate-source voltage of the first transistor.

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes: providing a semiconductor substrate; determining a position of a bit line contact opening on a top surface of the semiconductor substrate and a top surface of a first dielectric layer; etching an active region, the first dielectric layer and an isolation structure exposed by the bit line contact opening according to the position of the bit line contact opening until the active region is etched to a preset depth to form a bit line contact window; and forming a second dielectric layer on a surface of the isolation structure and a surface of the first dielectric layer that have a depth greater than a depth of a surface of the active region in the bit line contact window.

Abstract: This application relates to a machine learning model training method and apparatus, and an expression image classification method and apparatus. The machine learning model training method includes: obtaining a machine learning model that includes a model parameter and that is obtained through training according to a general-purpose image training set; determining a sample of a special-purpose image and a corresponding classification label; inputting the sample of the special-purpose image to the machine learning model, to obtain an intermediate classification result; and adjusting the model parameter of the machine learning model according to a difference between the intermediate classification result and the classification label, continuing training, and ending the training in a case that a training stop condition is met. The solutions provided in this application improve the training efficiency of the machine learning model.

Abstract: A method for manufacturing the semiconductor structure includes: providing a substrate, in which active regions and isolation regions are formed; forming grooves in the active regions, which include first grooves located at upper portions and second grooves located at lower portions and communicating with the first grooves, and a width of the first grooves is greater than a width of the second grooves; and forming gate structures in the first grooves and the second grooves.

Abstract: An electrical connector including an insulating body, a first metallic member, a second metallic member, a plurality of terminals, and a metallic shell is provided. The insulating body has a base portion, a thickened step portion, and a tongue portion. The thickened step portion is located at a root of the base portion. The first metallic member and the second metallic member are disposed on an upper surface and a lower surface of the insulating body. The metallic shell is disposed on an exterior of the insulating body to surround the first metallic member, the second metallic member, and the terminals, wherein the front flat contact portion of each of the terminals is exposed out of the tongue portion, and a portion of the first metallic member and a portion of the second metallic member are exposed out of the thickened step portion.

Abstract: This application provides a semiconductor switch device and a preparation method thereof, and a solid-state phase shifter. The semiconductor switch device includes a second semiconductor layer, a first intrinsic layer, a first semiconductor layer, a second intrinsic layer, and a third semiconductor layer that are stacked in a sandwich structure. The first intrinsic layer is located between the second semiconductor layer and the first semiconductor layer, and the first intrinsic layer, the second semiconductor layer, and the first semiconductor layer form a first PIN diode. The second intrinsic layer is located between the third semiconductor layer and the first semiconductor layer, and the second intrinsic layer, the third semiconductor layer, and the first semiconductor layer form a second PIN diode. The first PIN diode and the second PIN diode are axisymmetrically disposed.

Abstract: An electrical connector with HDMI 2.1 specification, including an insulating body, multiple terminals, and a metallic shell partially enclosing the insulating body and the terminals, is provided. The terminals include ten terminals located in an upper row and nine terminals located in a lower row. The ten terminals are sequentially a first terminal Data2+, a third terminal Data2?, a fifth terminal Data Shield, a seventh terminal Data0+, a ninth terminal Data0?, a eleventh terminal Data3 Shield, a thirteenth terminal CEC, a fifteenth terminal SCL, a seventeenth terminal DDC/CEC Ground, and a nineteenth terminal Hot Plug Detec1 along an arrangement direction. The nine terminals are sequentially a second terminal Data2 Shield, a fourth terminal Data1+, a sixth terminal Data1?, an eighth terminal Data0 Shield, a tenth terminal Data3+, a twelfth terminal Data3?, a fourteenth terminal Utility, a sixteenth terminal SDA, and an eighteenth terminal +5V Power along the arrangement direction.

Abstract: The present disclosure provides systems and methods for associating data with non-material concepts that allows for subsequent searching and retrieval of such non-material concepts. A concept definition is received that defines a concept identifier used for identifying data associated with the concept, and a plurality of discrete stages of the concept. Retrieved data is analyzed to determine if the data corresponds to the concept, and to determine at least one discrete stage of the concept definition that the data corresponds to. The data is stored in association with the concept identifier and the at least one discrete stage to allow for subsequent searching and retrieval. When a search request relating to the concept is received, the data associated with the different stages of the concept can be retrieved and output in a manner to capture the holistic nature of the concept.

Abstract: An electrical connector complied with HDMI 2.1 including an insulating body, multiple terminals, and a metallic shell enclosing portions of the insulating body and the terminals is provided. The ten terminals includes a first terminal Data2+, a third terminal Data2?, a fifth terminal Data Shield, a seventh terminal Data0+, a ninth terminal Data0?, an eleventh terminal Data3 Shield, a thirteenth terminal CEC, a fifteenth terminal SCL, a seventeenth terminal DDC/CEC Ground, and a nineteenth terminal Hot Plug Detec1 arranged in an arrangement direction in sequence. The nine terminals includes a second terminal Data2 Shield, a fourth terminal Data1+, a sixth terminal Data1?, an eighth terminal Data0 Shield, a tenth terminal Data3+, a twelfth terminal Data3?, a fourteenth terminal Utility, a sixteenth terminal SDA, and an eighteenth terminal +5V Power arranged in an arrangement direction in sequence.

Abstract: Embodiments relate to a semiconductor structure and a method for fabricating the same. The semiconductor structure includes: a base substrate including a trench, where the trench includes a gate structure whose top surface is lower than a top surface of the trench; first etch stop layers, where the first etch stop layers cover the top surface of the gate structure, part of a side wall of the trench, and an upper surface of the base substrate; an enclosed isolation structure positioned between the first etch stop layers in the trench, where the enclosed isolation structure at least plugs an opening of the trench; and an air gap positioned between the first etch stop layer and the enclosed isolation structure, where the air gap at least includes a transverse portion, and a bottom of the enclosed isolation structure is positioned on the transverse portion.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a channel groove, located in the substrate; and a fin, located on a bottom wall of the channel groove, wherein the fin protrudes towards an inner side of the channel groove, and a gap is provided between the fin and each sidewall of the channel groove, wherein the sidewall of the channel groove includes a connection surface and a step surface, and the step surface includes at least one step unit.

Abstract: A method for forming the active area includes the following operations. A semiconductor substrate is provided. A first mask layer and a second mask layer are sequentially formed on a surface of the semiconductor substrate, in which the second mask layer has an initial pattern for forming the active area. A sacrificial layer covering the second mask layer is formed. The sacrificial layer and a portion of the second mask layer are removed to form a third mask layer with a preset thickness, in which the preset thickness is less than an initial thickness of the second mask layer. The active area is formed through the third mask layer and the first mask layer.

Abstract: This application relates to a machine learning model training method and apparatus, and an expression image classification method and apparatus. The machine learning model training method includes: obtaining a machine learning model that includes a model parameter and that is obtained through training according to a general-purpose image training set; determining a sample of a special-purpose image and a corresponding classification label; inputting the sample of the special-purpose image to the machine learning model, to obtain an intermediate classification result; and adjusting the model parameter of the machine learning model according to a difference between the intermediate classification result and the classification label, continuing training, and ending the training in a case that a training stop condition is met. The solutions provided in this application improve the training efficiency of the machine learning model.