Abstract: A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and an enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. In response to the corresponding disabling logic level of the latched clock signal, the input latch is configured to hold a logic level of the latched output signal unchanged, regardless of the input signal having one or more logic level switchings, while the enable signal is having the disabling logic level.

Abstract: A circuit includes a series of a first latch circuit, selection circuit, second latch circuit, and pre-decoder. A control circuit, based on a clock signal, outputs control signals to the selection circuit and first and second latch circuits, and, to the pre-decoder, a pulse signal including a first pulse during a first portion of a clock period in response to a read enable signal having a first logical state, and a second pulse during a second portion of the clock period in response to a write enable signal having the first logical state. Based on the control signals, the selection circuit and first and second latch circuits output read and write addresses to the pre-decoder during the respective first and second clock period portions, and the pre-decoder outputs a partially decoded address in response to each of the read address and first pulse, and the write address and second pulse.

Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first P-type transistor coupled to the NAND logic gate, and configured to receive a first clock signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

Abstract: One or more systems, devices, computer program products and/or computer-implemented methods of use provided herein relate to training an AI model to predict status of a DBMS. The computer-implemented system can comprise a memory that can store computer executable components. The computer-implemented system can further comprise a processor that can execute the computer executable components stored in the memory, wherein the computer executable components can comprise a data ingestion component that can use testing data of an AI model to generate ingested data by randomly changing one or more records of at least one feature comprised in the testing data, wherein the ingested data can be used to compute a first ratio indicative of inequity of the at least one feature. The computer executable components can further comprise a training component that can train the AI model using at least the first ratio to predict a status of system.

Abstract: Provided are an essential oil composition and a preparation method thereof. The essential oil composition includes a eutectic composition and an essential oil; the eutectic composition includes a hydrogen-bond donor and a hydrogen-bond acceptor; the hydrogen-bond donor is geranic acid or derivatives of the geranic acid; the hydrogen-bond acceptor is choline or derivatives or hydrates of the choline; a mass ratio of the hydrogen-bond donor to the hydrogen-bond acceptor is 1-10:1-10.

Abstract: A memory device includes a memory array, a first latch and a first logic element. The memory array is configured to operate according to a first global write signal. The first latch is configured to generate a first latch write data based on a clock signal. The first logic element is configured to generate the first global write signal based on the clock signal and the first latch write data.

Abstract: One aspect of the present disclosure pertains to a method. The method includes receiving a first circuit structure having semiconductor devices, an interconnect structure, first feedthrough vias, top metal lines, redistribution vias, and bond pads. The method includes dicing the first circuit structure to form a top die having a top semiconductor device. The method includes forming a stacked integrated circuit (IC) structure by bonding the top die to a second circuit structure, the second circuit structure having second semiconductor devices, a second interconnect structure, second redistribution vias, and second bond pads. The method includes forming IC top metal lines over the first feedthrough vias, forming an IC passivation layer over the IC top metal lines, forming metal-insulator-metal (MIM) capacitor structures in the IC passivation layer, and forming IC redistribution vias penetrating through the MIM capacitor structures and the IC passivation layer to land on the IC top metal lines.

Abstract: The implementation of the present disclosure discloses a memory and its operation method, a memory system and an electronic device. The memory includes: a memory cell array and a page buffer, the page buffer is disposed corresponding to a bit line of the memory cell array, and the page buffer includes: a precharge and discharge circuit coupled to the bit line through a sense node of the page buffer and including a first type transistor; a plurality of latches respectively coupled to the sense node, wherein at least one of the plurality of latches includes a second type transistor, and a characteristic size of the second type transistor is smaller than that of the first type transistor.

Abstract: Embodiments of the present application disclose a semiconductor structure, a formation method thereof and a memory. The semiconductor structure includes: a substrate; a channel located in the substrate, the channel being configured to form a gate structure; and a convex portion arranged on an inner wall of the channel. The embodiments of the present application can increase a channel length and solve a short-channel effect.

Abstract: A display module and a display device are provided, the display module includes a backlight module and a display panel, which includes: a backplane, including a bottom plate and a side plate; an optical element arranged at a side of the bottom plate close to the display panel; a light-emitting element at a side of the side plate close to the optical element; a middle frame between the bottom plate and the display panel, the middle frame includes a first strip-shaped portion; a first included angle is formed between at least part of the first strip-shaped portion and a surface of the optical element close to the display panel; an orthographic projection of the first strip-shaped portion on the display panel at least overlaps with an orthographic projection of an edge of the optical element close to the light-emitting element on the display panel.

Abstract: The present disclosure discloses an active camera relocation method having robustness to illumination includes the following steps: extracting effective plane region image sets of scenes in a current observation image T and a reference observation image R; establishing a matching relationship in the effective plane region image sets T and R; obtaining a camera relative pose Pi guided by each group of matched planes; obtaining information for guiding the motion of a camera by fusing all camera relative poses Pi; determining whether a relocation process is completed by motion steps.

Abstract: Provided in the embodiments of the present application are a transform method, inverse transform method, encoder, decoder and storage medium.

Abstract: A current limiter and a charge pump regulator including the current limiter are provided. The charge pump regulator converts an input voltage to an output voltage and includes a feedback loop including a first transistor for regulating a discharge current from the charge pump regulator. The current limiter limits the current provided by the charge pump regulator. The current limiter includes a sampling block configured to sample a first drain-source voltage of the first transistor and hold it as a reference drain-source voltage; an adaptive tracking block configured to receive the reference drain-source voltage, and to generate a maximum voltage based on the reference drain-source voltage, so that the maximum voltage tracks the reference drain-source voltage; and a voltage clamp block configured to clamp a feedback voltage to the maximum voltage, and to provide the clamped voltage as a first gate-source voltage of the first transistor.

Abstract: A chamber of a semiconductor fabrication facility may include a vent port diffuser. The vent port diffuser may include a first tube member configured to couple the vent port diffuser to a vent port of the chamber. The vent port diffuser may include a second tube member coupled to the first tube member. The second tube member may comprise a plurality of openings spaced along a length of the second tube member, with the plurality of openings configured to receive a fluid from the chamber. Based on the semiconductor fabrication facility including the vent port diffuser, the chamber may be configured to provide an improved flow field of a fluid within the chamber. In this way, the vent port diffuser may reduce defects of semiconductor devices transported through the chamber that might otherwise be caused by contaminants.

Abstract: Methods and wafers for low etch pit density, low slip line density, and low strain indium phosphide are disclosed and may include an indium phosphide single crystal wafer having a diameter of 4 inches or greater, having a measured etch pit density of less than 500 cm?2, and having fewer than 5 dislocations or slip lines as measured by x-ray diffraction imaging. The wafer may have a measured etch pit density of 200 cm?2 or less, or 100 cm?2 or less, or 10 cm?2 or less. The wafer may have a diameter of 6 inches or greater. An area of the wafer with a measured etch pit density of zero may at least 80% of the total area of the surface. An area of the wafer with a measured etch pit density of zero may be at least 90% of the total area of the surface.

Abstract: The present invention discloses a traffic light timing control method and system, including the following steps: S1: completing monitoring of traffic flow, and recording and storing traffic flow data in each data collection gap; S2: dividing a historical dataset into a sample PA and a sample PB, and assigning a crowding level; S3: obtaining duration of a green light of each piece of traffic flow data separately; S4: generating a preliminary classification model according to the duration of the green light. In the present invention, the duration of a green light at different periods and under different crowd conditions can be dynamically adjusted and the duration of a data collection gap is also adjusted for an actual road condition, so that a green light timing control solution obtained finally can better meet an actual traffic control requirement.

Abstract: Provided are a method for predicting a colour component, an encoder and a decoder. The method includes: a first reference sample set of a colour component to be predicted of a current block is determined; a reference sample subset is determined from the first reference sample set, where the reference sample subset includes one or more candidate samples selected from the first reference sample set; and a model parameter of a prediction model is calculated according to positions of reference samples in the reference sample subset, where the prediction model is configured to perform prediction processing on the colour component to be predicted of the current block.

Abstract: Provided are an image component prediction method, an encoder and a decoder, said method comprising: determining a first reference pixel set of a colour component to be predicted of a current block; and calculating a model parameter of a prediction model according to positions of reference pixels in the first reference pixel set, the prediction model being configured to perform prediction processing on the colour component to be predicted of the current block.

Abstract: A method for picture prediction, an encoder, a decoder, and a storage medium are provided. The method includes the following. At least one colour component of a current block in a picture is determined. The at least one colour component of the current block is pre-processed to obtain at least one pre-processed colour component. A prediction model is constructed according to the at least one pre-processed colour component, where the prediction model is used to perform cross-component prediction on the at least one colour component of the current block.

Abstract: The present invention relates to bispecific anti-CCL2 antibodies binding to two different epitopes on human CCL2, pharmaceutical compositions thereof, their manufacture, and use as medicaments for the treatment of cancers, inflammatory, autoimmune and ophthalmologic diseases.