Patents by Inventor Wei Wang

Wei Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12225205
    Abstract: Systems and methods for block-wise entropy coding methods in neural image compression is provided. A method includes: receiving a bitstream that includes an image; partitioning the image into a plurality of blocks; compressing each of the plurality of blocks by a neural network-based encoder; obtaining compressed features by obtaining a compressed feature for each block from among the plurality of blocks in the image; processing the compressed features by an entropy encoder to generate a first compressed bitstream; obtaining a plurality of reshaped compressed features by concatenating the compressed features; processing the plurality of reshaped compressed features by the entropy encoder to generate a second compressed bitstream; and encoding the bitstream including the image based on the second compressed bitstream.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: February 11, 2025
    Assignee: TENCENT AMERICA LLC
    Inventors: Sheng Lin, Wei Jiang, Shan Liu, Wei Wang
  • Patent number: 12221673
    Abstract: Disclosed are an aluminum nitride-reinforced aluminum matrix composite (AMC) and a preparation method thereof, relating to the technical field of metal matrix composites (MMCs). The aluminum nitride-reinforced AMC includes the following components: Si, Mg, Nb, Zr, Mo, Zn, Ta, Mn, Cu, Co, In, B, Ge, Ir, a rare earth element, Sn, nano-titanium carbide, nano-chromium nitride, an aluminum nitride nanofiber, nano-aluminum nitride, Al, meso-tetramethyl-tetra-(p-aminophenyl) calix[4] pyrrole, sodium silicate, and 1,3,5-triglycidyl-S-triazinetrione.
    Type: Grant
    Filed: October 2, 2024
    Date of Patent: February 11, 2025
    Assignee: Inner Mongolia Metal Material Research Institute
    Inventors: Mingyi Zhang, Ping Gao, Wenlong Zhang, Zhicheng Shi, Wei Wang, Linyu Chen
  • Patent number: 12224246
    Abstract: A processing method of a flexible hybrid electronic system is provided and includes the following steps: etching out embedded grooves on a front surface of a silicon-based substrate embedding a plurality of heterogeneous chips into corresponding embedded grooves, wherein front surfaces of the embedded chips are flush with the front surface of the silicon-based substrate; then gradually realize the polymer flexible connection, electrical interconnection, insulation protection, and polymer flexible coverage between chips. The processing method processes the flexible hybrid electronic system based on the method of embedding chips, which can reduce material loss and processing steps, and is beneficial to realizing large-scale manufacturing.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: February 11, 2025
    Assignee: PEKING UNIVERSITY
    Inventors: Wei Wang, Lang Chen
  • Publication number: 20250046678
    Abstract: A method includes receiving a workpiece including a device layer disposed on a frontside of the workpiece, forming a frontside interconnect structure over the device layer, attaching a carrier substrate over the frontside interconnect structure, and etching from a backside of the workpiece to form first trenches and second trenches. The first trenches extend partially into the carrier substrate for a distance less than the second trenches. The method also includes forming a plurality of first conductive features in the first trenches and a plurality of second conductive features in the second trenches, forming a backside interconnect structure covering the first conductive features and the second conductive features, and thinning the carrier substrate from the frontside of the workpiece to expose the second conductive features. The first conductive features remain partially embedded in the carrier substrate.
    Type: Application
    Filed: January 8, 2024
    Publication date: February 6, 2025
    Inventors: Tsung-Chieh Hsiao, Ke-Gang Wen, Yu-Bey Wu, Liang-Wei Wang
  • Publication number: 20250048624
    Abstract: The present disclosure provides embodiments of electronic fuse devices. An electronic fuse device according to the present disclosure includes a first bit cell comprising a first plurality of active regions extending along a first direction and a second bit cell comprising a second plurality of active regions extending along the first direction. Each of the first plurality of active regions is aligned with one of the second plurality of active regions along the first direction. The first bit cell and the second bit cell are spaced apart along the first direction by a space and the space is free of a well tap cell.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 6, 2025
    Inventors: Jui-Lin Chen, Meng-Sheng Chang, Ping-Wei Wang
  • Publication number: 20250041543
    Abstract: An automatic dosage-controlled atomizer includes a medication atomizer and a respiration sensor. The respiration sensor includes a capacitive electrode assembly that has a varying capacitance correlated to a respiratory airflow from a user, a resonant circuit that generates a resonant signal based on the varying capacitance, a signal analyzing circuit that obtains a detected vital capacity value and a period time data piece related to a breathing cycle of the user based on a frequency variation of the resonant signal, and an atomization adjustment module that generates a cumulative effective inhaled dose value based on the detected vital capacity value and the period time data piece. The atomization adjustment module causes the medication atomizer to stop generation of an aerosol airflow when the cumulative effective inhaled dose value exceeds a predetermined dose threshold value.
    Type: Application
    Filed: January 8, 2024
    Publication date: February 6, 2025
    Applicant: National Tsing Hua University
    Inventors: Ting-Wei WANG, Shih-Hua NI
  • Publication number: 20250048649
    Abstract: A semiconductor device includes a sense amplifier, a first magnetic tunneling junction (MTJ) connected to the sense amplifier at a first distance, a second MTJ connected to the sense amplifier at a second distance, and a third MTJ connected to the sense amplifier at a third distance. Preferably, the first distance is less than the second distance, the second distance is less than the third distance, a critical dimension of the first MTJ is less than a critical dimension of the second MTJ, and the critical dimension of the second MTJ is less than a critical dimension of the third MTJ.
    Type: Application
    Filed: October 17, 2024
    Publication date: February 6, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wei Wang, Yi-An Shih, Huan-Chi Ma
  • Publication number: 20250048686
    Abstract: The present disclosure provides an integrated circuit (IC) structure that includes a semiconductor substrate having a frontside and a backside; a shallow trench isolation (STI) structure formed in the semiconductor substrate and defining an active region, wherein the STI structure includes a STI bottom surface, wherein the semiconductor substrate includes a substrate bottom surface, and wherein the STI bottom surface and the substrate bottom surface are coplanar; a field-effect transistor (FET) over the active region and formed on the frontside of the semiconductor substrate; and a backside dielectric layer disposed on the substrate bottom surface and the STI bottom surface.
    Type: Application
    Filed: January 11, 2024
    Publication date: February 6, 2025
    Inventors: Ping-Wei Wang, Gu-Huan Li, Jui-Lin Chen
  • Publication number: 20250046667
    Abstract: A method includes forming a device die including forming integrated circuits on a semiconductor substrate; and forming a thermally conductive pillar extending into the semiconductor substrate. A cooling medium is attached over and contacting the semiconductor substrate to form a package, wherein the cooling medium is thermally coupled to the thermally conductive pillar.
    Type: Application
    Filed: October 6, 2023
    Publication date: February 6, 2025
    Inventors: Tsung-Chieh Hsiao, Ke-Gang Wen, Chih-Pin Chiu, Hsin-Feng Chen, Yu-Bey Wu, Liang-Wei Wang, Dian-Hau Chen
  • Publication number: 20250048613
    Abstract: The present disclosure provides an IC structure that includes a semiconductor substrate having a SRAM region, an input/output and peripheral (IOP) region, and an edge region spanning tween the SRAM region and the IOP region; a STI structure formed on the semiconductor substrate and defining active regions; a SRAM cell formed within the SRAM region; and a backside dielectric layer disposed on a backside of the semiconductor substrate and landing on a bottom surface of the STI structure. The active regions are longitudinally oriented along a first direction; gates are formed on the semiconductor substrate and are evenly distributed with a pitch P along the first direction; the SRAM cell spans a first dimension Ds along the first direction; the edge region spans a second dimension De along the first direction; and a ratio De/Ds equals to 2 or is less than 2.
    Type: Application
    Filed: January 12, 2024
    Publication date: February 6, 2025
    Inventors: Jui-Lin Chen, Feng-Ming Chang, Ping-Wei Wang, Yu-Bey Wu
  • Publication number: 20250048612
    Abstract: An integrated circuit (IC) device has a memory region in which a plurality of memory cells is implemented. Each of the memory cells has a first dimension in a first horizontal direction. The IC device includes an edge region bordering the memory cell region in the first horizontal direction. The edge region has a second dimension in the first horizontal direction. The second dimension is less than or equal to about 4 times the first dimension. The IC device is formed by revising a first IC layout to generate a second IC layout. The second IC layout is generated by shrinking a dimension of the edge region in the first horizontal direction.
    Type: Application
    Filed: January 4, 2024
    Publication date: February 6, 2025
    Inventors: Jui-Lin Chen, Feng-Ming Chang, Ping-Wei Wang, Yu-Bey Wu, Chih-Ching Wang
  • Publication number: 20250046756
    Abstract: Interconnect structures for front-to-front stacked chips/dies and methods of fabrication thereof are disclosed herein. An exemplary system on integrated circuit (SoIC) includes a first die that is front-to-front bonded with a second die, for example, by bonding a first topmost metallization layer of a first frontside multilayer interconnect of the first die to a second topmost metallization layer of a second frontside multilayer interconnect of the second die. A through via extends partially through the first frontside multilayer interconnect of the first die, through a device layer of the first die, through a backside power rail of the first die, and through a carrier substrate. The backside power rail is between the carrier substrate and the device layer, and the backside power rail may be a portion of a backside multilayer interconnect of the first die. The through via may be connected to a redistribution layer (RDL) structure.
    Type: Application
    Filed: January 4, 2024
    Publication date: February 6, 2025
    Inventors: Tsung-Chieh Hsiao, Yi Ling Liu, Ke-Gang Wen, Yu-Bey Wu, Liang-Wei Wang
  • Publication number: 20250042478
    Abstract: A rocker panel for use in a vehicle, the rocker panel includes an outboard plate, an inboard plate, and a reinforcement structure. The reinforcement structure is disposed between the inboard plate and the outboard plate. The reinforcement structure includes one or more discrete steel tubes extending longitudinally between the outboard plate and the inboard plate.
    Type: Application
    Filed: October 25, 2024
    Publication date: February 6, 2025
    Inventors: Miao YU, Sobhan T. Nazari, Jimmy J. Zhang, Panagiotis Makrygiannis, Feng Zhu, Sajan G. Elengikal, Jun Hu, Erik Russel Anderson, Scott Stevens, Yu-Wei Wang
  • Patent number: 12217637
    Abstract: The present disclosure provides a display backplane and a preparation method therefor, and a display apparatus. The display backplane includes a plurality of display units, at least one display unit includes a pixel area and a light transmitting area, the pixel area is configured to perform image display and the light transmitting area is configured to transmit light; and in a plane perpendicular to the display backplane, the light transmitting area includes a substrate and a light transmitting structure layer arranged on the substrate, and the light transmitting structure layer is provided with light transmitting holes.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: February 4, 2025
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Yang Yue, Wei Wang, Ruoyu Ma, Shunhang Zhang, Chuanxiang Xu, Xiang Li, Yong Yu, Shi Shu, Qi Yao
  • Patent number: 12216869
    Abstract: Provided are a display panel and a display device. An isolation dam is provided in a peripheral area of the display panel. The display panel includes: a display functional layer comprising a plurality of display signal traces; and a touch-control functional layer comprising a plurality of touch-control signal traces. On the binding side, there are a first boundary and a second boundary, and a first trace area located between the first boundary and the second boundary, the first boundary is closer to the display area than the second boundary. In the first trace area, the touch-control signal trace is arranged along a first direction and are led out from the binding circuit and connected to the touch-control pattern via the isolation dam and the first trace area in sequence, the display signal trace is arranged along a second direction and intersects with the touch signal trace.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: February 4, 2025
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yi Qu, Zhiwen Chu, Yang Zhou, Lu Bai, Junxiu Dai, Xinxin Wang, Yi Zhang, Shun Zhang, Xin Chen, Yu Wang, Ping Wen, Yuanqi Zhang, Wei Wang
  • Patent number: 12218651
    Abstract: The present disclosure provides a method of preparing a radio frequency filter, including: a substrate; a supporting electrode protruded on a front surface of the substrate; and a thin film structure formed on the substrate and spaced with the substrate by the supporting electrode. An end surface of a top end of the supporting electrode is in sealing contact with a front surface of the thin film structure.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: February 4, 2025
    Assignee: Epicmems (Xiamen) Co., Ltd.
    Inventors: Jiang Jiang, Ping Li, Wei Wang, Mingguo Zhu, Nianchu Hu, Bin Jia
  • Patent number: 12213593
    Abstract: In one aspect of the invention, the adjustable bed includes a headboard assembly having a headboard and an upper rail attached to the headboard; a footboard assembly having a footboard and a lower rail attached to the footboard; a pair of sideboard assemblies having a pair of sideboards and a pair of side rails respectively attached to the pair of sideboards, wherein the pair of sideboard assemblies is transversely spaced and longitudinally aligned in parallel, and detachably attached to the headboard assembly and the footboard assembly; and a lifting mechanism attached to the side rails of the pair of sideboard assemblies for operably adjusting the adjustable bed at a desired position.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: February 4, 2025
    Assignee: NISCO CO., LTD
    Inventors: Wei Wang, Jian Xie, Yifan Mao
  • Patent number: 12216589
    Abstract: An apparatus has processing circuitry with support for transactional memory, and a cache hierarchy comprising at least two levels of cache. In response to a draining trigger event having potential to cause loss of state stored in at least one further level cache beyond a predetermined level cache in which speculative store data generated by a transaction is marked as speculative until the transaction is committed, draining circuitry performs a draining operation to scan a subset of the cache hierarchy to identify dirty cache lines and write data associated with the dirty cache lines to persistent memory. The subset of the cache hierarchy includes the at least one further level cache. In the draining operation, speculative store data marked as speculative in the predetermined level cache is prevented from being drained to the persistent memory.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: February 4, 2025
    Assignee: Arm Limited
    Inventors: Wei Wang, Matthew James Horsnell
  • Patent number: 12213594
    Abstract: An adjustable bed includes a frame structure having a first frame, a second frame, and a pair of connection bars detachably connecting the first frame and the second frame to one another; a plurality of platforms disposed on the frame structure; and an adjustable assembly coupled with the frame structure for operably adjusting one or more of the plurality of platforms in desired positions.
    Type: Grant
    Filed: October 11, 2022
    Date of Patent: February 4, 2025
    Assignee: NISCO CO., LTD
    Inventors: Wei Wang, Fahuan Zhang, Jian Xie, Yifan Mao
  • Patent number: 12215677
    Abstract: An artificial cilium device includes a substrate and a voltage-actuated cilia-shaped structure attached at a proximal end to the substrate. The voltage-actuated cilia-shaped structure has a first layer of a first material and a second layer of a second material. The second layer of the second material includes an exposed surface that causes the cilia-shaped structure to, in a working medium, (a) change shape from a first shape to a second shape responsive to application of a first voltage and (b) change shape from the second shape to the first shape responsive to application of a second voltage different than the first voltage.
    Type: Grant
    Filed: July 24, 2024
    Date of Patent: February 4, 2025
    Assignee: Cornell University
    Inventors: Itai Cohen, Wei Wang, Qingkun Liu