Abstract: A memory system includes a control block, an antifuse voltage generator, an array voltage generator, and a memory array. The control block is used to output control signals to the memory array according to a memory control data signal. The antifuse voltage generator is used to output an antifuse control signal to the memory array according to a control signal and a driving voltage. The array voltage generator is used to output a selection signal and a following control signal to the memory array according a control signal. The memory array is coupled to the control block, the antifuse voltage generator, and the array voltage generator and configured to access data according to the first control signal, the antifuse control signal, the selection signal, and the following control signal. The first control signal comprises address information of the memory array.

Abstract: A memory system includes a control block, an antifuse voltage generator, an array voltage generator, and a memory array. The control block is used to output control signals to the memory array according to a memory control data signal. The antifuse voltage generator is used to output an antifuse control signal to the memory array according to a control signal and a driving voltage. The array voltage generator is used to output a selection signal and a following control signal to the memory array according a control signal. The memory array is coupled to the control block, the antifuse voltage generator, and the array voltage generator and configured to access data according to the first control signal, the antifuse control signal, the selection signal, and the following control signal. The first control signal comprises address information of the memory array.

Abstract: The invention provides a flash memory apparatus including at least one flash memory array block and a sense amplifying module. The flash memory array block comprises N storage columns, N reference word-line cell units and a reference storage column, wherein N is a positive integer. Each of the reference word-line cell units disposed in each of the storage columns, wherein, the reference word-line cell units further coupled to a reference word line and a dummy word line. The reference storage column includes a plurality of reference bit-line cells, the reference word line and the dummy word line, one of the reference bit-line cells which coupled to the reference word line is coupled to a reference bit line. The sense amplifying module compares currents from one of the bit lines and the corresponding reference bit line to generate at least one sensing result.

Abstract: The invention provides a flash memory apparatus including at least one flash memory array block and a sense amplifying module. The flash memory array block comprises N storage columns, N reference word-line cell units and a reference storage column, wherein N is a positive integer. Each of the reference word-line cell units disposed in each of the storage columns, wherein, the reference word-line cell units further coupled to a reference word line and a dummy word line. The reference storage column includes a plurality of reference bit-line cells, the reference word line and the dummy word line, one of the reference bit-line cells which coupled to the reference word line is coupled to a reference bit line. The sense amplifying module compares currents from one of the bit lines and the corresponding reference bit line to generate at least one sensing result.

Abstract: A delay circuit and related apparatus for providing a longer delay time, such that when a level of an input signal changes, a level of an output signal changes accordingly after the predetermined delay time. The delay circuit has a storage unit, a current generator, a voltage generator for providing a reference voltage, a differential amplifier, and a feedback control module. The current generator starts to provide a charging current to the storage unit when the input signal changes level, such that an output charging voltage of the storages unit is gradually charged to reach the reference voltage. The feedback control module is capable of dynamically decreasing the charging current provided to the storage unit as the charging voltage is approaching the reference voltage, and the amplifier will change the level of the output voltage when the charging voltage reaches the reference voltage.

Abstract: A delay circuit and related apparatus for providing a longer delay time, such that when a level of an input signal changes, a level of an output signal changes accordingly after the predetermined delay time. The delay circuit has a storage unit, a current generator, a voltage generator for providing a reference voltage, a differential amplifier, and a feedback control module. The current generator starts to provide a charging current to the storage unit when the input signal changes level, such that an output charging voltage of the storages unit is gradually charged to reach the reference voltage. The feedback control module is capable of dynamically decreasing the charging current provided to the storage unit as the charging voltage is approaching the reference voltage, and the amplifier will change the level of the output voltage when the charging voltage reaches the reference voltage.

Abstract: A method for forming contact window is disclosed. Essential concept of the invention comprises over coating layer formed over surface before forming contact window is formed and the etching rate of over coating layer is higher than etching rate of underlying layer. The method comprises following steps: First, forming semiconductor structures on surface of wafer. Second, forming a coating layer over the surface and covering these semiconductor structures. Third, forming an over coating layer on the coating layer, where etching rate of over coating layer is higher than etching rate of coating layer. Finally, form contact window with outwardly winded shape. Thus, contact window formed by the invention is more convenient for filling material than contact window formed by conventional method. In addition, because width of contact window is not obviously increased, this invention is more beneficial for deep-submicron fabrication.

Abstract: A test key includes a substrate, a deep trench capacitor formed in the substrate, and at least one active region defined on the substrate. The active region comprises a first region, a second region and an ion well. A thermal oxide layer is formed in the first region. A top-thin oxide layer is formed in the second region. The second region overlaps with the deep trench capacitor. At least one word line partially overlapping with the top-thin oxide layer. The ion well is electrically connected with a polysilicon electrode of the deep trench capacitor. The thermal oxide layer within the first region does not overlap with any word line.

Abstract: A charge pump for a flash memory. The charge pump includes: a current-guiding circuit having a first, a second, and a third output; and a first, a second, and a third charge unit. The current-guiding circuit has two diode-connected transistors respectively connected between the first and the second outputs, and the second and the third outputs. Each of the charge units, for storing charge, has two ends. The first, the second, and the third charge units respectively have one end connected to the first, the second, and the third outputs, and the other end of the third charge unit is connected to the first output.

Abstract: This invention discloses a method for avoiding microscratch in interlevel dielectric layer chemical mechanical polishing process. There is step height difference on surface of the interlevel dielectric layer between the memory array and the logic device, so, the interlevel dielectric layer over the memory array is etched to form a sidewall and a corner. As a key step of this invention, a dielectric layer is capped over the interlevel dielectric layer to smooth the corner and avoid microscratch thereon when performing chemical mechanical polishing process.

Abstract: This invention discloses a method for avoiding microscratch in interlevel dielectric layer chemical mechanical polishing process. There is step height difference on surface of the interlevel dielectric layer between the memory array and the logic device, so, the interlevel dielectric layer over the memory array is etched to form a sidewall and a corner. As a key step of this invention, a dielectric layer is capped over the interlevel dielectric layer to smooth the corner and avoid microscratch thereon when performing chemical mechanical polishing process.

Abstract: A method of forming self-aligned suicide. An inter-poly dielectric layer is formed on a metal-oxide semiconductor to cover a source/drain region of the metal-oxide semiconductor, while a gate thereof is exposed. A metal layer is formed to cover the exposed gate and the inter-poly dielectric layer. Performing a rapid thermal process, the metal layer is reacted with the gate to form a silicide layer. The remaining metal layer which is not reacted with the gate and the inter-poly dielectric layer are then removed to expose the source/drain region. Another metal layer is formed to cover the source/drain region. Performing a rapid thermal process, the metal layer is reacted with the source/drain region to form another silicide layer.

Abstract: A method of manufacturing a bottom electrode of a capacitor. A substrate has a contact pad formed thereon, a first dielectric layer is formed on the contact pad, and a node contact penetrates through the first dielectric layer and electrically couples to the contact pad. A second dielectric layer is formed on the first dielectric layer and the node contact. A third dielectric layer is formed on the second dielectric layer. A fourth dielectric layer is formed on the third dielectric layer. A trench is formed to penetrate through the fourth, the third and the second dielectric layer and to expose a surface of the node contact. A conductive layer is formed on the fourth dielectric layer and a sidewall and a bottom of the trench. A fifth dielectric layer is formed on the conductive layer, wherein the fifth dielectric layer fills the trench. A portion of the fifth dielectric layer and a portion of the conductive layer are removed until a surface of the fourth dielectric layer is exposed.

Abstract: A method for forming contact window is disclosed. Essential concept of the invention comprises over coating layer formed over surface before forming contact window is formed and the etching rate of over coating layer is higher than etching rate of underlying layer. The method comprises following steps: First, forming semiconductor structures on surface of wafer. Second, forming a coating layer over the surface and covering these semiconductor structures. Third, forming an over coating layer on the coating layer, where etching rate of over coating layer is higher than etching rate of coating layer. Finally, form contact window with outwardly winded shape. Thus, contact window formed by the invention is more convenient for filling material than contact window formed by conventional method. In addition, because width of contact window is not obviously increased, this invention is more beneficial for deep-submicron fabrication.

Abstract: A method for fabricating a borderless contact is disclosed. The method includes providing a substrate with an active region and a trench formed therein. Then, the trench is etched to stop at a depth. A conformal stop layer is deposited on the substrate. As a key step, the stop layer is etched to form spacer against top corner of the trench. A dielectric layer is formed on the substrate. Then, an opening is etched in the dielectric layer to form a borderless contact, wherein the opening overlies both a portion of the trench and a portion of the active region.

Abstract: A method of enhancing chemical mechanical polishing uniformity is provided. In the fabrication of a shallow trench isolation structure, there are active area regions with different integration formed in a chip. The integration of the active area regions in the chip is computed according circuit designs by a program analysis. One of the active area regions with the highest integration is used as a basis, dummy mesas are formed in the other active area regions to adjust the integration of the chip.

Abstract: An ion implantation method useful for fabricating shallow trench isolation structureimplants phosphorus ions instead of arsenic ions into a substrate when the source/drain regions of an NMOS device are doped. Alternatively, low energy ions are used in the ion implantation for forming the source/drain regions of an NMOS device. Consequently lattice dislocations of the crystal structure within a substrate is reduced and unwanted device leakage current is eliminated.

Abstract: A self-aligned process for forming a silicide layer over word lines in DRAM and a silicide layer over transistors in a logic device region. A substrate that includes a memory cell region and a logic circuit region is provided. A first transistor and a second transistor are formed over the substrate. The first transistor is formed in the logic circuit region and includes a first gate conductive layer and a first source/drain region. The second transistor is formed in the memory cell region and includes a second gate conductive layer and a second source/drain region. A blocking layer is formed over both the first transistor and the second transistor. A portion of the blocking layer is removed to expose the first gate conductive layer, the first source/drain region and the second gate conductive layer. The remaining blocking layer still covers the second source/drain region. A metal silicide layer is formed over the first gate conductive layer, the first source/drain region and the second gate conductive layer.

Abstract: A method of forming a bottom electrode of a capacitor in a dynamic random access memory cell. The bottom electrode of the capacitor is formed on a semiconductor wafer, the semiconductor wafer includes a silicon substrate, and a first dielectric layer positioned on the silicon substrate having a contact hole extending down to the silicon substrate. The method includes the following steps: a first polysilicon layer is formed in the contact hole as a conductive plug. A second dielectric layer is then formed on the first dielectric layer. A vertical opening is formed in the second dielectric layer that extends down to the contact hole, and a pillar-shaped second polysilicon layer is formed in the opening, that the bottom end of the second polysilicon layer is electrically connected to the first polysilicon layer in the contact hole.

Abstract: A method of manufacturing a bottom electrode of a capacitor. A substrate has a contact pad formed thereon, a first dielectric layer is formed on the contact pad, and a node contact penetrates through the first dielectric layer and electrically couples to the contact pad. A second dielectric layer is formed on the first dielectric layer and the node contact. A third dielectric layer is formed on the second dielectric layer. A fourth dielectric layer is formed on the third dielectric layer. A trench is formed to penetrate through the fourth, the third and the second dielectric layer and to expose a surface of the node contact. A conductive layer is formed on the fourth dielectric layer and a sidewall and a bottom of the trench. A fifth dielectric layer is formed on the conductive layer, wherein the fifth dielectric layer fills the trench. A portion of the fifth dielectric layer and a portion of the conductive layer are removed until a surface of the fourth dielectric layer is exposed.