Abstract: Methods of measuring the depth of an object from two-dimensional images of the object. Such a method includes measuring first patch information from a first image in an image capture plane of an edge boundary of an object. The first image includes the edge boundary at a first state of defocus, and the first patch information includes boundaries, color, and blurriness of the first image. Second patch information is then measured from a second image in the image capture plane of the edge boundary. The second image includes the edge boundary at a second state of defocus, and the second patch information includes boundaries, color, and blurriness of the second image. A distance of the object from the image capture plane is then measured from differences in the first and second patch information based on differences of the edge boundary between the first and second states of defocus.

Abstract: A semiconductor device includes decks stacked over a semiconductor layer in a vertical direction. Each deck includes alternating word line layers and insulating layers. A gate line structure (GLS) extends through the word line layers and the insulating layers of the decks. A channel structure extends through the word line layers and the insulating layers of the decks. A sidewall of the GLS is discontinuous at a border between two neighboring decks, and a sidewall of the channel structure is discontinuous at an interface between two neighboring decks. The GLS includes a first GLS that includes a gate line slit, a second GLS that includes sub-GLSs spaced apart from each other in a horizontal direction, or a combination thereof.

Abstract: A MAP architecture includes a low-voltage digital module, a low-voltage analog module, and one or more high-voltage analog modules. The low-voltage digital module is communicatively connected to the digital signal bus for implementing digital functions, the low-voltage analog module is communicatively connected to the low-voltage digital module and the digital signal bus for implementing low-voltage analog functions, and the high-voltage analog modules are communicatively connected to one or more of the low-voltage digital module, the digital signal bus, and the low-voltage analog module for implementing high-voltage analog functions. The present disclosed MAP architecture integrates low-voltage and high-voltage analog functions required for applications such as energy-saving power control. These functions include power input, mixed-signal processing, and load driving. The integration of these functions allows users to reduce the construction of peripheral hardware analog circuits as much as possible.

Abstract: A robotic tool system includes a robotic tool and a navigation control device. The robotic tool system is used to move in a working area and perform a work task. The navigation control device is detachably connected with the robotic tool and includes a navigation assembly, a planning assembly and a communication assembly. The navigation assembly is used to receive a position signal of the robotic tool and/or the navigation control device. The planning assembly is used to obtain a path map of the working area by fitting according to the position signal. The communication assembly is connected with the robotic tool, transmits the path map to the robotic tool, controls the robotic tool to run in the working area according to the path map and performs corresponding task or return to a charger station to realize an automatic charging connection.

Abstract: Automatic generation of network signatures is disclosed. Network profiles for malware samples are generated. Network signature candidates are selected based on the network profiles. The network signature candidates are automatically evaluated to automatically generate a new set of network signatures. The new set of network signatures is distributed to a security device/service to enforce the new set of network signatures to detect malware.

Abstract: An implementation of a memory device includes a stack structure having alternating first layers and dielectric layers. The stack structure has a first surface and a second surface opposite to the first surface. First contact structures include a conductive material. The first contact structures penetrate from the first surface into the stack structure to be in contact respectively with a first portion of first layers. Second contact structures include a conductive material. Each of the second contact structures penetrates from the second surface into the stack structure to be in contact respectively with a remainder portion of conductive layers other than the first portion of the first layers.

Abstract: A packaging module includes a substrate layer disposed in a stacking manner, and a plurality of chip layers stacked on the substrate layer. The plurality of chip layers include a top chip layer, and the top chip layer is a chip layer furthest from the substrate layer in the plurality of chip layers. The top chip layer includes a first chip, a connection surface of the first chip faces the substrate layer, and the connection surface of the first chip is conductively connected to a chip of an adjacent chip layer by using a first conductor. The connection surface of the first chip faces the substrate layer, so that the first conductor connected to the first chip and another chip does not occupy additional space, to reduce the thickness of the packaging module, and facilitate miniaturization of the packaging module.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers, a landing structure and a contact structure. The gate layers and the insulating layers are stacked alternatingly, and form stair steps in a staircase region. The landing structure is disposed on a first gate layer of a first stair step of the stair steps in the staircase region. The landing structure includes an upper structure and an isolation stack between the upper structure and the first gate layer. The upper structure is etch-selective to a contact isolation layer that covers the staircase region. The contact structure extends through the contact isolation layer and the landing structure and is connected with the first gate layer of the first stair step.

Abstract: A moving-device fault detection method and system are in the technical field of fault detection. The method includes the steps of collecting a measurement signal of a target device (S10); performing fault type classification on the measurement signal on the basis of an autocorrelation characteristic (S20); on the basis of the classification result, selecting a corresponding fault diagnosis model (S30); and performing fault diagnosis on the basis of the selected fault diagnosis model and the measurement signal to obtain a diagnosis result (S40). On the basis of a fault type distinguishing result, adaptive diagnosis model selection is made to ensure that the selected diagnosis model is a fault detection model suitable for current signal feature rules.

Abstract: A dry, flowable additive composition for combination with a fertilizer that increases longevity of plant available nitrogen from the fertilizer while in the soil.

Abstract: The present disclosure relates to semiconductor devices and fabrication methods thereof. An example semiconductor device includes conductive layers. The conductive layers include a first conductive layer and a second conductive layer. The semiconductor device further includes an insulating structure over the first conductive layer and the second conductive layer. The insulating structure includes a first layer. A material of the first layer has a first etching rate smaller than an etching rate of an insulating material between the conductive layers. The semiconductor device further includes a first contact structure extending through a first portion of the first layer and connected to the first conductive layer. The semiconductor device further includes a second contact structure extending through a second portion of the first layer and connected to the second conductive layer.

Abstract: A method of forming a three-dimensional (3D) NAND memory device includes: forming a gate line slit through alternating layers of an oxide layer and a conductive material layer, wherein the conductive material layer is further formed on a sidewall and a bottom of the gate line slit; performing a first etch process to remove portions of the conductive material layer from the sidewall and the bottom of the gate line slit and from between adjacent oxide layers, thereby exposing portions of the oxide layer in the gate line slit; removing the exposed portions of the oxide layer on the sidewall of the gate line slit; and performing a second etch process to remove residues of the conductive material layer in the gate line slit.

Abstract: The present disclosure relates methods, devices, systems, and techniques for merging schemes in semiconductor devices such as three-dimensional (3D) semiconductor devices. In one aspect, a semiconductor device includes a semiconductor structure that includes a stack of conductive layers and insulating layers alternating with each other along a first direction. The semiconductor structure includes an array region and a connection region adjacent to the array region in a second direction perpendicular to the first direction. The semiconductor device further includes multiple contact structures extending through the connection region along the first direction. Each conductive layer in the stack of conductive layers and insulating layers is coupled to a corresponding contact structure of the multiple contact structures and isolated from one or more other contact structures of the multiple contact structures.

Abstract: The present disclosure provides flow cytometers, reagent cartridges, multi-well reagent and sample plates, and methods of analyzing a sample by flow cytometry using same.

Abstract: Methods, devices, systems, and techniques for managing conductive structure in semiconductor devices are provided. In one aspect, a semiconductor device includes a first memory cell including a first transistor having a first storage structure and a first semiconductor body and a second memory cell having a second storage structure and a second transistor having a second semiconductor body. The semiconductor device also includes a conductive structure that is between and in contact with the first semiconductor body and the second semiconductor body; a first contact structure including a first end and a second end, where the first end of the first contact structure is in contact with the conductive structure, and the second end of the first contact structure is between the first end and the first storage structure; and a second contact structure that is in contact with the first contact structure.

Abstract: A heterogeneous-binder electrode assembly and methods for forming electrodes for lithium-ion batteries are presented. The heterogeneous-binder electrode assembly includes a metal foil current collector, a non-porous layer adhered to the current collector that includes active material particles, a conductive agent, and a binder system containing carboxymethyl cellulose and styrene-butadiene rubber, and a porous carboxymethyl cellulose layer bonded to the non-porous layer to increase electrolyte infiltration and ion transport.

Abstract: A salt and a crystal form of a cycloalkene compound, and a preparation method therefor and the use thereof. Specifically, a salt and a crystal form of a compound as represented by general formula (I), a preparation method, and a pharmaceutical composition comprising a therapeutically effective amount of the salt, and the use thereof as a regulator in the preparation of a drug for treating metabolic diseases and related diseases.

Abstract: An uninterruptible power supply, a control method and a power supply system for normally starting the uninterruptible power supply and securing switch devices are provided. The uninterruptible power supply includes a first rectification circuit, a charge-discharge circuit, a bus capacitor, a first switch circuit and a second rectification circuit. The first rectification circuit is connected to the charge-discharge circuit, and is configured to rectify a voltage outputted by the alternating current power supply. The charge-discharge circuit is connected to the bus capacitor, and is configured to charge the bus capacitor after boosting the voltage outputted by the first rectification circuit, until the voltage across the bus capacitor reaches a first voltage. The first switch circuit is connected to the second rectification circuit, and is configured to connect the alternating current power supply to the second rectification circuit.

Abstract: In some examples, the semiconductor structures include a stack structure, a plurality of conductive structures and a first insulating layer. The stack structure may include a plurality of first dielectric layers and gate layers which are alternately disposed; the stack structure may have a memory region and a connection region, the stack structure in the connection region may include a plurality of first dielectric layers and second dielectric layers. The plurality of conductive structures may be disposed in the connection region. The conductive structure includes conductive portions insulated from each other, each conductive portion penetrates through part of the stack structure and is connected with the gate layers. Parts of the conductive portions that penetrate through the stack structure may be disposed in a nested manner. The semiconductor structure is applied to a three-dimensional memory, so as to implement reading and writing operations of data. Other examples are disclosed.