Patents by Inventor Wei-Yu Chen

Wei-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250118716
    Abstract: A semiconductor package includes a semiconductor element, at least one electronic die, at least one optical die, an encapsulant, and a substrate. The semiconductor element has a first side and a second side opposing to the first side. The at least one electronic die is disposed over the first side. The at least one optical die is disposed over the first side and next to the at least one electronic die. The encapsulant is disposed on the first side and covers the at least one electronic die, where a sidewall of the at least one optical die is distant from the encapsulant, and a sidewall of the encapsulant is aligned with a sidewall of the semiconductor element. The substrate is disposed over the second side, where the at least one electronic die is electrically coupled to the substrate and the at least one optical die through the semiconductor element.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, Cheng-Shiuan Wong, Chia-Shen Cheng, Hsuan-Ting Kuo, Hao-Jan Pei, Hsiu-Jen Lin
  • Publication number: 20250117360
    Abstract: A processing apparatus includes a processing resource including a general-purpose parallel processing engine and a matrix accelerator. The matrix accelerator includes first circuitry to receive a command to perform operations associated with an instruction, second circuitry to configure the matrix accelerator according to a physical depth of a systolic array within the matrix accelerator and a logical depth associated with the instruction, third circuitry to read operands for the instruction from a register file associated with the systolic array, fourth circuitry to perform operations for the instruction via one or more passes through one or more physical pipeline stages of the systolic array based on a configuration performed by the second circuitry, and fifth circuitry to write output of the operations to the register file associated with the systolic array.
    Type: Application
    Filed: October 30, 2024
    Publication date: April 10, 2025
    Applicant: Intel Corporation
    Inventors: Jorge Parra, Wei-yu Chen, Kaiyu Chen, Varghese George, Junjie Gu, Chandra Gurram, Guei-Yuan Lueh, Stephen Junkins, Subramaniam Maiyuran, Supratim Pal
  • Publication number: 20250116847
    Abstract: An optical photographing lens assembly includes, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element and a sixth lens element. The first lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof. The second lens element has refractive power. The third lens element has refractive power. The fourth lens element has refractive power. The fifth lens element with refractive power has an image-side surface being convex in a paraxial region thereof, wherein an object-side surface and the image-side surface of the fifth lens element are both aspheric. The sixth lens element with refractive power has an object-side surface and an image-side surface being both aspheric. The optical photographing lens assembly has a total of six lens elements with refractive power.
    Type: Application
    Filed: December 19, 2024
    Publication date: April 10, 2025
    Inventor: Wei-Yu CHEN
  • Patent number: 12272886
    Abstract: An antenna device includes a differential-line, a first metal and a second metal. The differential-line includes a first line and a second line. The first metal and second metal are coupled to the first line and second line respectively. The first metal and second metal have different shapes and/or different sizes. The first metal and second metal form symmetric or asymmetric dipole. The first metal and second metal can be disposed on the same plane or different planes, can be electrically insulated and can have a first slot and a second slot respectively. The antenna device can further include a base coupled to the first line and second line. The base can be a daughter board having a front-end module or not. The IC package in daughter board can have different sizes. The daughter board can be offset by different distances and can be coupled to a mother board.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: April 8, 2025
    Assignee: IWAVENOLOGY CO., LTD.
    Inventors: Chong-Yi Liou, Wei-Ting Tsai, Jin-Feng Neo, Zheng-An Peng, Tsu-Yu Lo, Zhi-Yao Hong, Tso-An Shang, Je-Yao Chang, Chien-Bang Chen, Shih-Ping Huang, Shau-Gang Mao
  • Patent number: 12271006
    Abstract: Disclosed is a cost-effective method to fabricate a multifunctional collimator structure for contact image sensors to filter ambient infrared light to reduce noises. In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; a plurality of via holes; and a conductive layer, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, and wherein the conductive layer is formed over at least one of the following: the first surface of the first dielectric layer and a portion of sidewalls of each of the plurality of via holes, and wherein the conductive layer is configured so as to allow the optical collimator to filter light in a range of wavelengths.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Yu Chen, Yen-Chiang Liu, Jiun-Jie Chiou, Jia-Syuan Li, You-Cheng Jhang, Shin-Hua Chen, Lavanya Sanagavarapu, Han-Zong Pan, Chun-Peng Li, Chia-Chun Hung, Ching-Hsiang Hu, Wei-Ding Wu, Jui-Chun Weng, Ji-Hong Chiang, Hsi-Cheng Hsu
  • Patent number: 12265773
    Abstract: The present disclosure provides a method and an apparatus for testing a semiconductor device. The method includes providing an active area in an integrated circuit design layout; grouping the active area into a first region and a second region; calculating a first self-heating temperature of the first region of the active area; calculating a second self-heating temperature of the second region of the active area; and determining an Electromigration (EM) evaluation based on the first self-heating temperature and the second self-heating temperature.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: April 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsien Yu Tseng, Wei-Ming Chen
  • Patent number: 12257612
    Abstract: An apparatus includes a wafer stage and a particle removing assembly. The wafer stage includes a cup adjacent to a wafer chuck. The particle removing assembly is configured to remove contaminant particles from the cup. In some embodiments, the particle removing assembly comprises a flexible ejecting member that includes one or more elongated tubes, a front tip, and a cleaning tip adapter configured to attach the front tip to each of the one or more elongated tubes. The front tip includes front openings and lateral openings from which pressurized cleaning material are introduced onto an unreachable area of the cup to remove the contaminant particles from the cup.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: March 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Hsueh Wu, Fang Yu Kuo, Kai Yu Liu, Yu-Chun Wu, Jau-Sheng Huang, Wei-Yi Chen
  • Publication number: 20250096092
    Abstract: A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.
    Type: Application
    Filed: November 28, 2024
    Publication date: March 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Yu Yeh, Tsung-Shu Lin, Wei-Cheng Wu, Tsung-Yu Chen, Li-Han Hsu, Chien-Fu Tseng
  • Patent number: 12255219
    Abstract: Some embodiments are directed towards an image sensor device. A photodetector is disposed in a semiconductor substrate, and a transfer transistor is disposed over photodetector. The transfer transistor includes a transfer gate having a lateral portion extending over a frontside of the semiconductor substrate and a vertical portion extending to a first depth below the frontside of the semiconductor substrate. A gate dielectric separates the lateral portion and the vertical portion from the semiconductor substrate. A backside trench isolation structure extends from a backside of the semiconductor substrate to a second depth below the frontside of the semiconductor substrate. The backside trench isolation structure laterally surrounds the photodetector, and the second depth is less than the first depth such that a lowermost portion of the vertical portion of the transfer transistor has a vertical overlap with an uppermost portion of the backside trench isolation structure.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Chi Hung, Dun-Nian Yaung, Jen-Cheng Liu, Wei Chuang Wu, Yen-Yu Chen, Chih-Kuan Yu
  • Publication number: 20250087652
    Abstract: A semiconductor package includes an interposer that has a first side and a second side opposing the first side. A semiconductor device that is on the first side of the interposer and an optical device that is on the first side of the interposer and next to the semiconductor device. A first encapsulant layer includes a first portion and a second portion. The first portion of the first encapsulant layer is on the first side of the interposer and along sidewalls of the semiconductor device. A gap is between a first sidewall of the optical device and a second sidewall of the first portion of the first encapsulant layer. A substrate is over the second side of the interposer. The semiconductor device and the optical device are electrically coupled to the substrate through the interposer.
    Type: Application
    Filed: January 5, 2024
    Publication date: March 13, 2025
    Inventors: Wei-Yu Chen, Cheng-Shiuan Wong, Chia-Shen Cheng, Hsuan-Ting Kuo, Hao-Jan Pei, Hsiu-Jen Lin, Mao-Yen Chang
  • Publication number: 20250085512
    Abstract: An optical lens system includes nine lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element, a seventh lens element, an eighth lens element and a ninth lens element. At least one lens surface of the seventh lens element, the eighth lens element and the ninth lens element has at least one critical point in an off-axis region thereof, and each of the seventh lens element, the eighth lens element and the ninth lens element has at least one lens surface being aspheric.
    Type: Application
    Filed: November 21, 2024
    Publication date: March 13, 2025
    Applicant: LARGAN PRECISION CO., LTD.
    Inventor: Wei-Yu CHEN
  • Publication number: 20250088658
    Abstract: Methods and apparatuses for video coding are provided. A method includes signaling a first syntax element for determining whether information of one or more reference picture lists is present in a picture header (PH) associated with a picture; and signaling the information of the one or more reference picture lists in the PH in a case that the first syntax element has a first value, wherein in a case that the information of the one or more reference picture lists is signaled in the PH and one or more slices associated with the picture are determined, from the information of the one or more reference picture lists, as being not bi-predictive, one or more second syntax elements in the PH are not parsed.
    Type: Application
    Filed: November 25, 2024
    Publication date: March 13, 2025
    Applicant: BEIJING DAJIA INTERNET INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Yi-Wen CHEN, Xiaoyu XIU, Tsung-Chuan MA, Hong-Jheng JHU, Wei CHEN, Xianglin WANG, Bing YU
  • Patent number: 12248126
    Abstract: A photographing optical lens assembly includes seven lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. The first lens element has negative refractive power. The third lens element has positive refractive power. The fourth lens element has negative refractive power. The sixth lens element has an image-side surface being convex in a paraxial region thereof. The seventh lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof. The image-side surface of the seventh lens element has at least one critical point in an off-axis region thereof. There is an air gap in a paraxial region between all adjacent lens elements of the seven lens elements.
    Type: Grant
    Filed: April 3, 2024
    Date of Patent: March 11, 2025
    Assignee: LARGAN PRECISION CO., LTD.
    Inventor: Wei-Yu Chen
  • Patent number: 12250411
    Abstract: Methods and apparatuses for video coding are provided. The method includes that a decoder determines whether a disable flag is present in a picture header (PH) associated with a picture, wherein the disable flag specifies whether a coding tool is disabled in one or more slices associated with the PH. Additionally, the method includes that the decoder infers value of the disable flag according to one or more enable flags signaled in a sequence parameter set (SPS) of the picture in response to determining that the disable flag is not present in the PH, inferring, by the decoder.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: March 11, 2025
    Assignee: BEIJING DAJIA INTERNET INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Yi-Wen Chen, Xiaoyu Xiu, Tsung-Chuan Ma, Hong-Jheng Jhu, Wei Chen, Xianglin Wang, Bing Yu
  • Publication number: 20250078573
    Abstract: A gesture recognition method includes steps of (S1) capturing a current image; (S2) determining whether the image includes a hand image; (S3) when a determination result of step S2 is satisfied, determining whether the hand image is a valid gesture; (S4) when a determination result of step S3 is satisfied, the gesture recognition unit records multiple coordinate information and time information of multiple locations corresponding to multiple fingers in a finger list, and storing the finger list in the storage unit; (S5) the gesture recognition unit obtaining an orientation of the palm; (S6) the gesture recognition unit calculating a width of the palm and a dynamic displacement threshold; (S7) the gesture recognition unit determining whether to launch an action command according to the orientation of the palm, the dynamic displacement threshold, and a determination condition; (S8) when the determination result of step S7 is satisfied, launching the action command.
    Type: Application
    Filed: October 13, 2023
    Publication date: March 6, 2025
    Inventors: Wei-De Hsing, Chia-Nan Pan, Guan-Yu Chen
  • Publication number: 20250081668
    Abstract: A chip package includes a semiconductor substrate, an anti-reflection layer, and a metal multi-layer. The semiconductor substrate has an optical sensing area. The anti-reflection layer is located on the semiconductor substrate. The metal multi-layer is located on and in contact with the anti-reflection layer. The metal multi-layer includes a redistribution line and two probe pads. Two ends of the redistribution line respectively extend to the two probe pads. The redistribution line is located in the optical sensing area, and the two probe pads are located outside the optical sensing area. The orthographic projection area of the redistribution line in the optical sensing area is less than 1% of the area of the optical sensing area.
    Type: Application
    Filed: August 13, 2024
    Publication date: March 6, 2025
    Inventors: Wei-Luen SUEN, Po-Jung CHEN, Jiun-Yen LAI, Tsang Yu LIU
  • Publication number: 20250080742
    Abstract: Methods and devices are provided for reducing the decoding latency introduced by LMCS. In one method, during encoding of a coding unit (CU), a plurality of reconstructed luma samples is selected from a first pre-determined region neighboring to a second pre-determined region where the CU is located, an average of the plurality of reconstructed luma samples is calculated, and the average of the plurality of reconstructed luma samples is used directly, without any clipping, in deriving a chroma residual scaling factor, a bitstream comprising luma mapping with chroma scaling (LMCS) related information is formed.
    Type: Application
    Filed: October 11, 2024
    Publication date: March 6, 2025
    Applicant: BEIJING DAJIA INTERNET INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Xiaoyu XIU, Yi-Wen CHEN, Tsung-Chuan MA, Hong-Jheng JHU, Wei CHEN, Xianglin WANG, Bing YU
  • Publication number: 20250076245
    Abstract: A method and system for establishing a model for sensing ions in a solution, and a method and system for sensing ions in a solution apply an ion-sensitive field effect transistor in a machine learning model for ion detection in training solutions. The method for establishing a model includes adjusting environmental parameters, where the environmental parameters are selected from any one of multiple target temperatures or from any one of multiple external electric fields; establishing at least one virtual sensor based on the biasing relationship of the multi-gate ion sensitive field effect transistor; obtaining, by the at least one virtual sensor, multiple training features of the training solution based on the environmental parameters and bias parameters; and loading, by a computer, the environmental parameters and the training features into a machine learning model to establish an ion detection model, which is used to sense the types and concentrations of ions.
    Type: Application
    Filed: November 9, 2023
    Publication date: March 6, 2025
    Inventors: Chih-Ting Lin, Yi-Ting Wu, Sheng-Yu Chen, Wei-En Hsu
  • Patent number: 12245412
    Abstract: A device includes first and second gate electrodes, a word line and a first metal island. The first gate electrode corresponds to transistors of a memory cell. The second gate electrode is separated from the first gate electrode and corresponds to the transistors. The word line is coupled to the memory cell and located between the first and the second gate electrodes. The first metal island is configured to couple a first power supply to the memory cell. A first boundary of the first metal island is located between first and second boundaries of the first gate electrode and is located between first and second boundaries of the word line, and each of the first boundary of the first gate electrode and the first boundary of the word line is located between first and second boundaries of the first metal island.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hidehiro Fujiwara, Wei-Min Chan, Chih-Yu Lin, Yen-Huei Chen, Hung-Jen Liao
  • Publication number: 20250070077
    Abstract: A system for reflowing a semiconductor workpiece including a stage, a first vacuum module and a second vacuum module, and an energy source is provided. The stage includes a base and a protrusion connected to the base, the stage is movable along a height direction of the stage relative to the semiconductor workpiece, the protrusion operably holds and heats the semiconductor workpiece, and the protrusion includes a first portion and a second portion surrounded by and spatially separated from the first portion. The first vacuum module and the second vacuum module respectively coupled to the first portion and the second portion of the protrusion, and the first vacuum module and the second vacuum module are operable to respectively apply a pressure to the first portion and the second portion. The energy source is disposed over the stage to heat the semiconductor workpiece held by the protrusion of the stage.
    Type: Application
    Filed: November 7, 2024
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Shiuan Wong, Ching-Hua Hsieh, Hsiu-Jen Lin, Hao-Jan Pei, Hsuan-Ting Kuo, Wei-Yu Chen, Chia-Shen Cheng, Philip Yu-Shuan Chung