Patents by Inventor Wei-Yu Chen

Wei-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240363426
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate, at least two gate structures disposed over the substrate, each of the at least two gate structures including a gate electrode and a spacer disposed along sidewalls of the gate electrode, wherein the spacer includes a refill portion and a bottom portion, the refill portion of the spacer has a funnel shape such that a top surface of the refill portion of the spacer is larger than a bottom surface of the refill portion of the spacer, and a source/drain contact disposed over the substrate and between the spacers of the at least two gate structures.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Cheng-Yu Yang, Yen-Ting Chen, Wei-Yang Lee, Fu-Kai Yang, Yen-Ming Chen
  • Publication number: 20240364886
    Abstract: An electronic apparatus performs a method of coding video data. The method comprises: receiving, from the bitstream, syntax elements associated with a coding unit, wherein the syntax elements include a first coded block flag (CBF) for residual samples of a first chroma component, a second CBF for residual samples of a second chroma component, and a third syntax element indicating whether adaptive color transform (ACT) is applied to the coding unit; determining whether to perform the chroma residual scaling to the residual samples of the chroma components according to the first CBF, the second CBF, and the third syntax element; in accordance with a determination to perform the chroma residual scaling to the residual samples of the first and second chroma components, scaling the residual samples of the at least one of the first and second chroma components based on a corresponding scaling parameter.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Xiaoyu XIU, Yi-Wen CHEN, Tsung-Chuan MA, Hong-Jheng JHU, Wei CHEN, Che-Wei KUO, Xianglin WANG, Bing YU
  • Publication number: 20240363388
    Abstract: An adhesion film with a plurality of semiconductor packages thereupon may be positioned on a pedestal including an enclosure and having a perforated top surface, a first support ring located at a periphery of the perforated top surface, and a second support ring laterally surrounding the first support ring. A first semiconductor package overlaps segments of the first support ring at a plurality of overlap areas in a top-down view, and does not contact the second support ring in the top-down view. A vacuum suction may be applied to a volume within the enclosure and to a gap which is vertically bounded by a bottom surface of the adhesion film and is laterally bounded by the first support ring while holding the first semiconductor package stationary. A portion of the adhesion film underlying the first semiconductor package is peeled off a bottom surface of the first semiconductor package.
    Type: Application
    Filed: April 26, 2023
    Publication date: October 31, 2024
    Inventors: Hsin Liang Chen, Ching-Hua Hsieh, Hsiu-Jen Lin, Hsuan-Ting Kuo, Wei-Yu Chen, Cheng-Shiuan Wong
  • Publication number: 20240364885
    Abstract: An electronic apparatus performs a method of coding video data. The method comprises: receiving, from the bitstream, syntax elements associated with a coding unit, wherein the syntax elements include a first coded block flag (CBF) for residual samples of a first chroma component, a second CBF for residual samples of a second chroma component, and a third syntax element indicating whether adaptive color transform (ACT) is applied to the coding unit; determining whether to perform the chroma residual scaling to the residual samples of the chroma components according to the first CBF, the second CBF, and the third syntax element; in accordance with a determination to perform the chroma residual scaling to the residual samples of the first and second chroma components, scaling the residual samples of the at least one of the first and second chroma components based on a corresponding scaling parameter.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Xiaoyu XIU, Yi-Wen CHEN, Tsung-Chuan MA, Hong-Jheng JHU, Wei CHEN, Che-Wei KUO, Xianglin WANG, Bing YU
  • Publication number: 20240363576
    Abstract: A semiconductor package structure includes a semiconductor die encapsulated in a molding compound, a redistribution structure over the semiconductor die and the molding compound, a surface device over and electrically connected to the redistribution structure, a first connector over and electrically connected to the redistribution structure, a second connector between the surface device and the redistribution structure, a trench in the redistribution structure and laterally surrounding the surface device in a top view of the semiconductor package structure, and an underfill. The second connector electrically connects the surface device to the redistribution structure. The underfill surrounds the second connector. The underfill include a first portion and a second portion. The first portion of the underfill is located between the surface device and the redistribution structure and laterally surrounding the second connector, and the second portion of the underfill is disposed in the trench.
    Type: Application
    Filed: April 25, 2023
    Publication date: October 31, 2024
    Inventors: WEI-YU CHOU, YANG-CHE CHEN, YI-LUN YANG, TING-YUAN HUANG, HSIANG-TAI LU
  • Publication number: 20240364884
    Abstract: An electronic apparatus performs a method of coding video data. The method comprises: receiving, from the bitstream, syntax elements associated with a coding unit, wherein the syntax elements include a first coded block flag (CBF) for residual samples of a first chroma component, a second CBF for residual samples of a second chroma component, and a third syntax element indicating whether adaptive color transform (ACT) is applied to the coding unit; determining whether to perform the chroma residual scaling to the residual samples of the chroma components according to the first CBF, the second CBF, and the third syntax element; in accordance with a determination to perform the chroma residual scaling to the residual samples of the first and second chroma components, scaling the residual samples of the at least one of the first and second chroma components based on a corresponding scaling parameter.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Xiaoyu XIU, Yi-Wen CHEN, Tsung-Chuan MA, Hong-Jheng JHU, Wei CHEN, Che-Wei KUO, Xianglin WANG, Bing YU
  • Publication number: 20240361609
    Abstract: Disclosed is a method to fabricate a multifunctional collimator structure In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; and a plurality of via holes, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, wherein the substrate has a bulk impurity doping concentration equal to or greater than 1×1019 per cubic centimeter (cm?3) and a first thickness, and wherein the bulk impurity doping concentration and the first thickness of the substrate are configured so as to allow the optical collimator to filter light in a range of wavelengths.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Hsin-Yu CHEN, Chun-Peng LI, Chia-Chun HUNG, Ching-Hsiang HU, Wei-Ding WU, Jui-Chun WENG, Ji-Hong CHIANG, Yen Chiang LIU, Jiun-Jie CHIOU, Li-Yang TU, Jia-Syuan LI, You-Cheng JHANG, Shin-Hua CHEN, Lavanya SANAGAVARAPU, Han-Zong PAN, Hsi-Cheng HSU
  • Publication number: 20240363676
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The magnetic element has multiple sub-layers, and each sub-layer is wider than another sub-layer above it. The semiconductor device structure also includes an isolation layer extending exceeding edges the magnetic element, and the isolation layer contains a polymer material. The semiconductor device structure further includes a conductive line over the isolation layer and extending exceeding the edges of the magnetic element.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Cheng CHEN, Wei-Li HUANG, Chun-Yi WU, Kuang-Yi WU, Hon-Lin HUANG, Chih-Hung SU, Chin-Yu KU, Chen-Shien CHEN
  • Publication number: 20240363421
    Abstract: The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Yu LIN, Szu-Hua Chen, Kuan-Kan Hu, Kenichi Sano, Po-Cheng Wang, Wei-Yen Woon, Pinyen Lin, Che Chi Shih
  • Patent number: 12133323
    Abstract: A transmission device for suppressing the glass-fiber effect includes a circuit board and a transmission line. The circuit board includes a plurality of glass fibers, so as to define a fiber pitch. The transmission line is disposed on the circuit board. The transmission line includes a plurality of non-parallel segments. Each of the non-parallel segments of the transmission line has an offset distance with respect to a reference line. The offset distance is longer than or equal to a half of the fiber pitch.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: October 29, 2024
    Assignees: UNIMICRON TECHNOLOGY CORP., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chin-Hsun Wang, Ruey-Beei Wu, Ching-Sheng Chen, Chun-Jui Huang, Wei-Yu Liao, Chi-Min Chang
  • Publication number: 20240352187
    Abstract: A polymer, which is a composition of a battery, includes a polyester. The polyester is polymerized by at least two monomers, wherein each of the at least two monomers is selected from a group consisting of a carbonate ester and a polyol. The polyester can further include an end-capped polycarbonate ester, and the end-capped polycarbonate ester includes an inert group on an end thereof.
    Type: Application
    Filed: April 11, 2024
    Publication date: October 24, 2024
    Inventors: Wei-Yuan CHEN, Po-Tsun CHEN, Rih-Sian CHEN, Yi-Rou LU, Chia-Ying LI, Cheng-Yu TSAI, Chun-Hung TENG
  • Publication number: 20240355707
    Abstract: An integrated circuit device includes a first-type active-region semiconductor structure extending and a second-type active-region semiconductor structure both extending in a first direction. The second-type active-region semiconductor structure is stacked with the first-type active-region semiconductor structure. The integrated circuit device also includes a front-side conductive layer above the two active-region semiconductor structures and a back-side conductive layer below the two active-region semiconductor structures. The integrated circuit device still includes a front-side power rail extending in the second direction in the front-side conductive layer and a back-side power rail extending in the second direction in the back-side conductive layer. The integrated circuit device further includes a first source conductive segment connected to the front-side power rail and a second source conductive segment connected to the back-side power rail.
    Type: Application
    Filed: April 21, 2023
    Publication date: October 24, 2024
    Inventors: Yung-Chin HOU, Li-Chun TIEN, Chih-LIang CHEN, Chi-Yu LU, Wei-Cheng LIN, Guo-Huei WU
  • Publication number: 20240357341
    Abstract: An electronic device is provided. The electronic device includes a first subscriber identity module (SIM), a second SIM, and a processor. The processor is configured to merge a first signal from the first SIM and a second signal from the second SIM and transmit the first signal and the second signal through a radio frequency front end (RFFE) transmission path concurrently, in response to a determination that the first signal and the second signal are intra-band signals and the first SIM and the second SIM share one RFFE transmission path.
    Type: Application
    Filed: March 13, 2024
    Publication date: October 24, 2024
    Inventors: Kun-Lin WU, Wei-Yu CHEN
  • Publication number: 20240355912
    Abstract: A memory device comprises a source region, a drain region, a channel region, a gate dielectric layer, an MTJ stack, and a metal gate. The source region and the drain region are over a substrate. The channel region is between the source region and the drain region. The gate dielectric layer is over the channel region. The MTJ stack is over the gate dielectric layer. The MTJ stack comprises a first ferromagnetic layer, a second ferromagnetic layer with a switchable magnetization, and a tunnel barrier layer between the first and second ferromagnetic layers. The metal gate is over the MTJ stack.
    Type: Application
    Filed: July 1, 2024
    Publication date: October 24, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Ya-Jui TSOU, Wei-Jen CHEN, Pang-Chun LIU, Chee-Wee LIU, Shao-Yu LIN, Chih-Lin WANG
  • Patent number: 12125809
    Abstract: A method includes forming signal lines in a pair of neighboring metal layers of a semiconductor device, and forming first dummy conductive cells in an empty area without metal lines passing therethrough, between the pair of neighboring metal layers. At least two dummy conductive cells of the first dummy conductive cells that are separated from each other, and the at least two dummy conductive cells fully overlap one of the signal lines in plan view.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yu Ma, Hui-Mei Chou, Kuo-Ji Chen
  • Publication number: 20240348785
    Abstract: Methods for video decoding and encoding, apparatuses and non-transitory computer-readable storage media thereof are provided. In one method for video decoding, a binary arithmetic decoder may obtain, according to an adaptive weight, a multi-hypothesis probability for a binary symbol of a context model for the binary arithmetic decoder, where the multi-hypothesis probability indicates a probability of the binary symbol equaling to a binary value, and the binary symbol is from a plurality of binary symbols associated with the context model. Furthermore, the decoder may decode the binary symbol according to the multi-hypothesis probability.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 17, 2024
    Applicant: BEIJING DAJIA INTERNET INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Xiaoyu XIU, Yi-Wen CHEN, Wei CHEN, Han GAO, Che-Wei KUO, Hong-Jheng JHU, Ning YAN, Xianglin WANG, Bing YU
  • Publication number: 20240348777
    Abstract: Methods, apparatuses, and non-transitory computer-readable storage mediums are provided for video coding. In one method, a decoder obtains a first signaled flag that indicates whether a template-based intra mode derivation (TIMD) mode is applied on a current video block; and in response to determining that the TIMD mode is applied on the current video block based on the first signaled flag, the decoder obtains a second signaled flag in transform block (TB), coding block (CB), slice, picture, or sequence level that indicates whether signaling of an index of a template for TIMD is enabled, where the index of the template is signaled to derive the intra prediction mode for the current video block.
    Type: Application
    Filed: June 25, 2024
    Publication date: October 17, 2024
    Applicant: BEIJING DAJIA INTERNET INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Hong-Jheng JHU, Xiaoyu XIU, Yi-Wen CHEN, Wei CHEN, Che-Wei KUO, Ning YAN, Han GAO, Xianglin WANG, Bing YU
  • Publication number: 20240347479
    Abstract: A semiconductor package includes a package substrate having a top surface and an opposing bottom surface. The package substrate includes a top build-up wiring layer and an upper dielectric layer covering the top build-up wiring layer. A semiconductor device and a passive component are mounted on the top surface of the package substrate in a side-by-side manner. A molding compound encapsulates the semiconductor device and the passive component on the top surface of the package substrate. A cavity is disposed between the passive component and the top surface of the package substrate.
    Type: Application
    Filed: March 20, 2024
    Publication date: October 17, 2024
    Applicant: MEDIATEK INC.
    Inventors: Chu-Chia Chang, Pei-Haw Tsao, Peng-Yu Huang, Yu-Liang Hsiao, Wei-Fan Chen
  • Publication number: 20240345941
    Abstract: A core test method, for testing a processing circuit with multi cores, comprising: (a) testing defects of the cores to determine at least one failed core; (b) recording the failed core; (c) performing a performance test to all of the cores to generate performance data; and (d) filtering the performance data based on the failed core recorded in the step (b).
    Type: Application
    Filed: May 2, 2023
    Publication date: October 17, 2024
    Applicant: MediaTek Singapore Pte. Ltd.
    Inventors: Jianguo Ren, Hung-Yu Chiou, Cheng-Tien Wan, Chao-Yang Yeh, Wei-Lien Chen, Man-Yun Su, Zemin Xu, Wen-Hao Hsueh, Wei-Chuan Liu
  • Patent number: 12117596
    Abstract: An image lens assembly includes five lens elements, which are, in order from an object side to an image side along an optical path, a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element has positive refractive power. The third lens element has negative refractive power. The fourth lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof and an image-side surface being convex in a paraxial region thereof. The fifth lens element has an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof. The image-side surface of the fifth lens element includes at least one convex critical point in an off-axis region thereof.
    Type: Grant
    Filed: October 16, 2023
    Date of Patent: October 15, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Chung-Yu Wei, Hung-Shuo Chen, Kuan-Chun Wang, Wei-Yu Chen