Patents by Inventor Wei-Yu Chen

Wei-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250149488
    Abstract: In an embodiment, a method includes forming a device region along a first substrate; forming an interconnect structure over the device region and the first substrate; forming a metal pillar over the interconnect structure, forming the metal pillar comprising: forming a base layer over the interconnect structure; forming an intermediate layer over the base layer; and forming a capping layer over the intermediate layer; forming a solder region over the capping layer; and performing an etch process to recess sidewalls of the base layer and the capping layer from sidewalls of the intermediate layer and the solder region.
    Type: Application
    Filed: February 23, 2024
    Publication date: May 8, 2025
    Inventors: Wei-Yu Chen, Chao-Wei Chiu, Hsin Liang Chen, Hao-Jan Shih, Hao-Jan Pei, Hsiu-Jen Lin
  • Publication number: 20250140757
    Abstract: A chip package structure is provided. The chip package structure includes a wiring structure. The chip package structure includes a first chip structure over the wiring structure. The chip package structure includes a first molding layer surrounding the first chip structure. The chip package structure includes a second chip structure over the first chip structure and the first molding layer. The chip package structure includes a second molding layer surrounding the second chip structure and over the first chip structure and the first molding layer. The chip package structure includes a third chip structure over the second chip structure and the second molding layer. The chip package structure includes a third molding layer surrounding the third chip structure and over the second chip structure and the second molding layer. The chip package structure includes a fourth molding layer surrounding the second molding layer and the third molding layer.
    Type: Application
    Filed: December 31, 2024
    Publication date: May 1, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yu CHEN, An-Jhih SU
  • Patent number: 12283492
    Abstract: A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die.
    Type: Grant
    Filed: January 2, 2024
    Date of Patent: April 22, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen
  • Patent number: 12282429
    Abstract: An apparatus includes a processor core and a memory hierarchy. The memory hierarchy includes main memory and one or more caches between the main memory and the processor core. A plurality of hardware pre-fetchers are coupled to the memory hierarchy and a pre-fetch control circuit is coupled to the plurality of hardware pre-fetchers. The pre-fetch control circuit is configured to compare changes in one or more cache performance metrics over two or more sampling intervals and control operation of the plurality of hardware pre-fetchers in response to a change in one or more performance metrics between at least a first sampling interval and a second sampling interval.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: April 22, 2025
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Elnaz Ebrahimi, Ehsan Khish Ardestani Zadeh, Wei-Yu Chen, Liang Peng
  • Publication number: 20250118716
    Abstract: A semiconductor package includes a semiconductor element, at least one electronic die, at least one optical die, an encapsulant, and a substrate. The semiconductor element has a first side and a second side opposing to the first side. The at least one electronic die is disposed over the first side. The at least one optical die is disposed over the first side and next to the at least one electronic die. The encapsulant is disposed on the first side and covers the at least one electronic die, where a sidewall of the at least one optical die is distant from the encapsulant, and a sidewall of the encapsulant is aligned with a sidewall of the semiconductor element. The substrate is disposed over the second side, where the at least one electronic die is electrically coupled to the substrate and the at least one optical die through the semiconductor element.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, Cheng-Shiuan Wong, Chia-Shen Cheng, Hsuan-Ting Kuo, Hao-Jan Pei, Hsiu-Jen Lin
  • Publication number: 20250117360
    Abstract: A processing apparatus includes a processing resource including a general-purpose parallel processing engine and a matrix accelerator. The matrix accelerator includes first circuitry to receive a command to perform operations associated with an instruction, second circuitry to configure the matrix accelerator according to a physical depth of a systolic array within the matrix accelerator and a logical depth associated with the instruction, third circuitry to read operands for the instruction from a register file associated with the systolic array, fourth circuitry to perform operations for the instruction via one or more passes through one or more physical pipeline stages of the systolic array based on a configuration performed by the second circuitry, and fifth circuitry to write output of the operations to the register file associated with the systolic array.
    Type: Application
    Filed: October 30, 2024
    Publication date: April 10, 2025
    Applicant: Intel Corporation
    Inventors: Jorge Parra, Wei-yu Chen, Kaiyu Chen, Varghese George, Junjie Gu, Chandra Gurram, Guei-Yuan Lueh, Stephen Junkins, Subramaniam Maiyuran, Supratim Pal
  • Publication number: 20250116847
    Abstract: An optical photographing lens assembly includes, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element and a sixth lens element. The first lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof. The second lens element has refractive power. The third lens element has refractive power. The fourth lens element has refractive power. The fifth lens element with refractive power has an image-side surface being convex in a paraxial region thereof, wherein an object-side surface and the image-side surface of the fifth lens element are both aspheric. The sixth lens element with refractive power has an object-side surface and an image-side surface being both aspheric. The optical photographing lens assembly has a total of six lens elements with refractive power.
    Type: Application
    Filed: December 19, 2024
    Publication date: April 10, 2025
    Inventor: Wei-Yu CHEN
  • Patent number: 12266559
    Abstract: A method of handling a workpiece includes the following steps. A workpiece is placed on a chuck body, wherein the workpiece includes a tape carrier extending beyond a periphery of the chuck body and a workpiece body disposed on the tape carrier, and the chuck body includes a seal ring surrounding the periphery of the chuck body; the tape carrier is clamped outside the chuck body, wherein the tape carrier leans against the seal ring and an enclosed space is formed between the chuck body, the tape carrier and the seal ring; and a vacuum seal is formed by evacuating gas from the enclosed space to pull the periphery of the workpiece toward the chuck body.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Shiuan Wong, Chih-Chiang Tsao, Chao-Wei Chiu, Hao-Jan Pei, Wei-Yu Chen, Hsiu-Jen Lin, Ching-Hua Hsieh, Chia-Shen Cheng
  • Publication number: 20250087652
    Abstract: A semiconductor package includes an interposer that has a first side and a second side opposing the first side. A semiconductor device that is on the first side of the interposer and an optical device that is on the first side of the interposer and next to the semiconductor device. A first encapsulant layer includes a first portion and a second portion. The first portion of the first encapsulant layer is on the first side of the interposer and along sidewalls of the semiconductor device. A gap is between a first sidewall of the optical device and a second sidewall of the first portion of the first encapsulant layer. A substrate is over the second side of the interposer. The semiconductor device and the optical device are electrically coupled to the substrate through the interposer.
    Type: Application
    Filed: January 5, 2024
    Publication date: March 13, 2025
    Inventors: Wei-Yu Chen, Cheng-Shiuan Wong, Chia-Shen Cheng, Hsuan-Ting Kuo, Hao-Jan Pei, Hsiu-Jen Lin, Mao-Yen Chang
  • Publication number: 20250085512
    Abstract: An optical lens system includes nine lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element, a seventh lens element, an eighth lens element and a ninth lens element. At least one lens surface of the seventh lens element, the eighth lens element and the ninth lens element has at least one critical point in an off-axis region thereof, and each of the seventh lens element, the eighth lens element and the ninth lens element has at least one lens surface being aspheric.
    Type: Application
    Filed: November 21, 2024
    Publication date: March 13, 2025
    Applicant: LARGAN PRECISION CO., LTD.
    Inventor: Wei-Yu CHEN
  • Patent number: 12248126
    Abstract: A photographing optical lens assembly includes seven lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. The first lens element has negative refractive power. The third lens element has positive refractive power. The fourth lens element has negative refractive power. The sixth lens element has an image-side surface being convex in a paraxial region thereof. The seventh lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof. The image-side surface of the seventh lens element has at least one critical point in an off-axis region thereof. There is an air gap in a paraxial region between all adjacent lens elements of the seven lens elements.
    Type: Grant
    Filed: April 3, 2024
    Date of Patent: March 11, 2025
    Assignee: LARGAN PRECISION CO., LTD.
    Inventor: Wei-Yu Chen
  • Publication number: 20250068423
    Abstract: Described herein is a graphics processor comprising first circuitry configured to execute a decoded instruction and second circuitry configured to second circuitry configured to decode an instruction into the decoded instruction. The second circuitry is configured to determine a number of registers within a register file that are available to a thread of the processing resource and decode the instruction based on that number of registers.
    Type: Application
    Filed: August 22, 2023
    Publication date: February 27, 2025
    Applicant: Intel Corporation
    Inventors: Jorge Eduardo Parra Osorio, Jiasheng Chen, Supratim Pal, Vasanth Ranganathan, Guei-Yuan Lueh, James Valerio, Pradeep Golconda, Brent Schwartz, Fangwen Fu, Sabareesh Ganapathy, Peter Caday, Wei-Yu Chen, Po-Yu Chen, Timothy Bauer, Maxim Kazakov, Stanley Gambarin, Samir Pandya
  • Publication number: 20250070077
    Abstract: A system for reflowing a semiconductor workpiece including a stage, a first vacuum module and a second vacuum module, and an energy source is provided. The stage includes a base and a protrusion connected to the base, the stage is movable along a height direction of the stage relative to the semiconductor workpiece, the protrusion operably holds and heats the semiconductor workpiece, and the protrusion includes a first portion and a second portion surrounded by and spatially separated from the first portion. The first vacuum module and the second vacuum module respectively coupled to the first portion and the second portion of the protrusion, and the first vacuum module and the second vacuum module are operable to respectively apply a pressure to the first portion and the second portion. The energy source is disposed over the stage to heat the semiconductor workpiece held by the protrusion of the stage.
    Type: Application
    Filed: November 7, 2024
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Shiuan Wong, Ching-Hua Hsieh, Hsiu-Jen Lin, Hao-Jan Pei, Hsuan-Ting Kuo, Wei-Yu Chen, Chia-Shen Cheng, Philip Yu-Shuan Chung
  • Publication number: 20250067963
    Abstract: An imaging optical lens system includes eight lens elements which are, in order from an object side to an image side along an optical path: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element, a seventh lens element and an eighth lens element. The first lens element has positive refractive power. The second lens element has negative refractive power. The seventh lens element has an image-side surface being concave in a paraxial region thereof, and the image-side surface of the seventh lens element has at least one convex critical point in an off-axis region thereof.
    Type: Application
    Filed: November 12, 2024
    Publication date: February 27, 2025
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Kuan-Ting YEH, Wei-Yu CHEN
  • Patent number: 12236903
    Abstract: A display device and a backlight control method of the display device are provided. When a duration of an image occlusion period is shorter than a preset duration, a backlight driving circuit is controlled to respectively provide a first pulse current and a second pulse current in a first light emitting period and a second light emitting period in each frame period, so as to drive a backlight unit to provide a first backlight and a second backlight. Here, the first pulse current is greater than the second pulse current.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: February 25, 2025
    Assignee: Qisda Corporation
    Inventors: Chun-Chang Wu, Yi-Zong Jhan, Jen-Hao Liao, Tse-Wei Fan, Wei-Yu Chen, Fu-Tsu Yen, Feng-Lin Chen
  • Publication number: 20250060567
    Abstract: A photographing optical lens system includes seven lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. Each of the seven lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The object-side surface of the first lens element is convex in a paraxial region thereof. The seventh lens element has negative refractive power. The object-side surface of the seventh lens element is concave in a paraxial region thereof. At least one of all lens surfaces of the seven lens elements is aspheric and has at least one inflection point.
    Type: Application
    Filed: October 31, 2024
    Publication date: February 20, 2025
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Tzu-Chieh KUO, Wei-Yu CHEN
  • Patent number: 12230597
    Abstract: A package structure is provided. The package structure includes a semiconductor chip and a protective layer laterally surrounding the semiconductor chip. The package structure also includes a polymer-containing element over the protective layer. The protective layer is wider than the polymer-containing element.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: February 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Chih-Chiang Tsao, Wei-Yu Chen, Hsiu-Jen Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Publication number: 20250054892
    Abstract: A package structure including a first substrate and a second substrate is provided. The first substrate includes first bumps with first lateral dimension and second bumps with second lateral dimension. The first bumps are distributed in a first region of the first substrate, and the second bumps are distributed in the second region of the first substrate, wherein the first lateral dimension is greater than the second lateral dimension, and a first bump height of the first bumps is smaller than a second bump height of the second bumps. The second substrate includes conductive terminals electrically connected to the first bumps and the second bumps.
    Type: Application
    Filed: January 4, 2024
    Publication date: February 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Wei Chiu, Wei-Yu Chen, Hsin Liang Chen, Hao-Jan Shih, Hsiu-Jen Lin, Ching-Hua Hsieh
  • Patent number: 12224108
    Abstract: A coil module is provided, including a second coil mechanism. The second coil mechanism includes a third coil assembly and a second base corresponding to the third coil assembly. The second base has a positioning assembly corresponding to a first coil mechanism.
    Type: Grant
    Filed: October 5, 2023
    Date of Patent: February 11, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Feng-Lung Chien, Tsang-Feng Wu, Yuan Han, Tzu-Chieh Kao, Chien-Hung Lin, Kuang-Lun Lee, Hsiang-Hui Hsu, Shu-Yi Tsui, Kuo-Jui Lee, Kun-Ying Lee, Mao-Chun Chen, Tai-Hsien Yu, Wei-Yu Chen, Yi-Ju Li, Kuei-Yuan Chang, Wei-Chun Li, Ni-Ni Lai, Sheng-Hao Luo, Heng-Sheng Peng, Yueh-Hui Kuan, Hsiu-Chen Lin, Yan-Bing Zhou, Chris T. Burket
  • Publication number: 20250044551
    Abstract: An imaging optical lens assembly includes five optical elements with refractive power. The five optical elements, in order from an object side to an image side along an optical path, are a first optical element, a second optical element, a third optical element, a fourth optical element, and a fifth optical element. The first optical element has an object-side surface being concave in a paraxial region thereof. The third optical element has negative refractive power.
    Type: Application
    Filed: October 22, 2024
    Publication date: February 6, 2025
    Inventors: Shao-Yu CHANG, Wei-Yu CHEN