Patents by Inventor Wei-Yu Chen

Wei-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240387645
    Abstract: The present disclosure describes a semiconductor device and a method for forming the semiconductor device. The method includes forming a fin structure on a substrate, forming a gate structure on the fin structure, and forming a source/drain (S/D) region on the fin structure not covered by the gate structure. The method further includes forming a contact structure on the S/D region. Forming the contact structure includes forming a transition metal chalcogenide (TMC) layer on the S/D region, and forming a contact plug on the TMC layer.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Wei-Yen Woon, Cheng-Ming Lin, Han-Yu Lin, Szu-Hua Chen
  • Publication number: 20240388730
    Abstract: Methods, apparatuses, and non-transitory computer-readable storage mediums are provided for video decoding. In one method, a decoder determines a coding bit depth for at least one sample in a bitstream; the decoder determines a value of a first Sequence Parameter Set (SPS) flag for the at least one sample; and the decoder further determines a second SPS flag for the at least one sample based on the value of the first SPS flag in combination of a coding bit depth for the at least one sample.
    Type: Application
    Filed: July 8, 2022
    Publication date: November 21, 2024
    Applicant: BEIJING DAJIA INTERNET INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Hong-Jheng JHU, Xiaoyu XIU, Yi-Wen CHEN, Wei CHEN, Chen-Wei KUO, Ning YAN, Xianglin WANG, Bing YU
  • Publication number: 20240387184
    Abstract: A method of manufacturing a semiconductor device includes reducing a thickness of a device wafer bonded to a carrier wafer, wherein the device wafer includes a device, a portion of the carrier wafer beyond the device, in a plan view, is called a non-bonding area, and a portion of the carrier wafer overlapping the device, in the plan view, is called a device area. The method further includes performing an etching process on the non-bonding area of the carrier wafer, wherein the etching process is performed completely outside the device area of the carrier wafer.
    Type: Application
    Filed: May 19, 2023
    Publication date: November 21, 2024
    Inventors: Yan-Yu CHEN, Wei Tse HSU
  • Publication number: 20240387509
    Abstract: An integrated circuit including: substrates stacked one over another, the substrates including first to fourth substrates having a P-type doping; the first substrate including a first set of electrical components on one or more of the substrates and forming a first circuit; a first ground reference rail connected to the first circuit; a first power supply rail connected between the first power supply rail and the first ground reference rail; a first electrostatic discharge (ESD) conduction element, connected between the first ground reference rail and a first part of a common ground reference rail, including a first diode in the second substrate and a second diode in the first substrate; the first diode and the second diode being connected in parallel, having different dopant types and having opposite polarities; and a second part of the common ground reference rail being connected to the third substrate and the fourth substrate.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Wei Yu MA, Chia-Hui CHEN, Kuo-Ji CHEN
  • Publication number: 20240387397
    Abstract: An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region.
    Type: Application
    Filed: July 27, 2024
    Publication date: November 21, 2024
    Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
  • Publication number: 20240387621
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a first spacer on a bit line, wherein the first spacer includes low-k material doped with carbon. An oxidation process is performed to the first spacer such that a surface portion of the first spacer is transformed to an oxide spacer. The first spacer has a remaining first spacer that is not oxidized by the oxidation process. Then, a second spacer is formed on the oxide spacer, wherein the second spacer includes nitride. The oxide spacer is removed to form a gap between the remaining first spacer and the second spacer. A cover layer is formed to cover the bit line, the remaining first spacer, and the second spacer such that an air gap is sealed by the cover layer, the remaining first spacer, and the second spacer.
    Type: Application
    Filed: May 17, 2023
    Publication date: November 21, 2024
    Inventor: Wei Yu CHEN
  • Publication number: 20240387431
    Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Wei-Yu Chen, Li-Hsien Huang, An-Jhih Su, Hsien-Wei Chen
  • Publication number: 20240387180
    Abstract: The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Meng-Han Chou, Kuan-Yu Yeh, Wei-Yip Loh, Hung-Hsu Chen, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240386179
    Abstract: The present disclosure provides a method and an apparatus for testing a semiconductor device. The method includes providing an active area in an integrated circuit design layout; grouping the active area into a plurality of regions, each of the regions including at least one polysilicon gate; calculating an operating temperature of the at least one polysilicon gate in each of the regions; calculating a self-heating temperature of each of the regions based on the operating temperature of the at least one polysilicon gate in each of the regions; determining an Electromigration (EM) evaluation based on the self-heating temperatures of the regions; and generating a semiconductor device based on the integrated circuit design layout passing the EM evaluation, wherein one of the regions includes a number of polysilicon gates disposed thereon different from the number of polysilicon gates disposed on the rest of regions.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: HSIEN YU TSENG, WEI-MING CHEN
  • Publication number: 20240387219
    Abstract: An overhead transport vehicle is described for association with an Automated Material Handling System (AMHS). The overhead transport vehicle provides features to the AMHS by which the AMHS is able to reduce a number of manual urgent lot rescues by the fab operator when a logistic algorithm controlling traffic in the AMHS is unable to transport the front opening unified pods (FOUP) from one tool to the subsequent tool in the sequence of the process steps within the q-time due to unexpected problems. An indicator on the overhead transport vehicle which helps the fab operator with spotting a lot in trouble is described. A backup power source on the overhead transport vehicle used in case of a main power failure is also described.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Yen Le LEE, Yen-Yu CHEN, Wei Chih CHEN, Tai Hsiang LIAO, Kai-Ping CHAN
  • Publication number: 20240387412
    Abstract: A method includes forming signal lines in a pair of neighboring metal layers of a semiconductor device, and forming first dummy conductive cells in an empty area without metal lines passing therethrough, between the pair of neighboring metal layers. At least two dummy conductive cells of the first dummy conductive cells that are separated from each other, and the at least two dummy conductive cells fully overlap one of the signal lines in plan view.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yu MA, Hui-Mei CHOU, Kuo-Ji CHEN
  • Publication number: 20240387147
    Abstract: A cantilever for gas flow direction control configured to support an electrode housing bowl in an associated etch process chamber. The cantilever may have a cross-section that is circular, elliptical, or airfoil shaped. The shape of the cantilever induces the flow of gas and etch products within the chamber around the cantilever, reducing turbulence around the edge of a wafer.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Chien-Liang Chen, Chien-Yu Wang, Wei-Da Chen, Yu-Ning Cheng, Shih-tsung Chen, Yung-Yao Lee
  • Patent number: 12150243
    Abstract: A package assembly includes a substrate, an electronic component and a cover. The electronic component and the cover are disposed on the substrate, wherein the electronic component is located within a chamber between the cover and the substrate. A cooling liquid may be filled in a heat dissipation space of the cover, so as to dissipate the heat generated by the electronic component. Furthermore, the cooling liquid may be filled in the chamber where the electronic component is located, so as to directly dissipate the heat generated by the electronic component.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: November 19, 2024
    Assignee: Wiwynn Corporation
    Inventors: Yi Cheng, Wei-Ching Chang, Kang-Bin Mah, Li-Wei Chen, Zi-Ping Wu, Ting-Yu Pai
  • Patent number: 12149698
    Abstract: Methods and devices are provided for reducing the decoding latency introduced by LMCS. In one method, during decoding of a coding unit (CU), a plurality of reconstructed luma samples is selected from a first pre-determined region neighboring to a second pre-determined region where the CU is located, an average of the plurality of reconstructed luma samples is calculated, and the average of the plurality of reconstructed luma samples is used directly, without any clipping, in deriving a chroma residual scaling factor for decoding the CU.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: November 19, 2024
    Assignee: BEIJING DAJIA INTERNET INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Xiaoyu Xiu, Yi-Wen Chen, Tsung-Chuan Ma, Hong-Jheng Jhu, Wei Chen, Xianglin Wang, Bing Yu
  • Patent number: 12148236
    Abstract: Optical sensors and their making methods are described herein. In some embodiments, a described sensing apparatus includes: an image sensor; a collimator above the image sensor, wherein the collimator includes an array of apertures; and an optical filtering layer above the collimator, wherein the optical filtering layer is configured to filter a portion of light to be transmitted into the array of apertures.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: November 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: You-Cheng Jhang, Han-Zong Pan, Wei-Ding Wu, Jiu-Chun Weng, Hsin-Yu Chen, Cheng-San Chou, Chin-Min Lin
  • Patent number: 12148782
    Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: November 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Chuang Wu, Dun-Nian Yaung, Feng-Chi Hung, Jen-Cheng Liu, Jhy-Jyi Sze, Keng-Yu Chou, Yen-Ting Chiang, Ming-Hsien Yang, Chun-Yuan Chen
  • Publication number: 20240376303
    Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Photoresist layer is selectively exposed to radiation, and selectively exposed photoresist layer developed. Photoresist composition includes photoactive compound, crosslinker, copolymer.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-hao CHEN, Wei-Han LAI, Ching-Yu CHANG
  • Publication number: 20240379672
    Abstract: A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
  • Patent number: 12144065
    Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Da Cheng, Hsiu-Jen Lin, Cheng-Ting Chen, Wei-Yu Chen, Chien-Wei Lee, Chung-Shi Liu
  • Patent number: D1051830
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: November 19, 2024
    Assignee: HTC Corporation
    Inventors: Wei-Hsin Chang, Yi-Shen Wang, Hung-Yu Chen