Patents by Inventor Wei-Yu Chen

Wei-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12144075
    Abstract: A lighting device connects to an external power supply and includes a light emitting load and a secondary load. A temperature measurement is obtained related to a temperature of the external power supply. The secondary load is activated, thereby allowing the secondary load to be powered by the external power supply, when the temperature measurement is below a threshold. Thus, in cold conditions, an increased load is presented to the external power supply to assist start up of the external power supply in cold conditions.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: November 12, 2024
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Wei Li, Yuanqiang Liu, Meiping Mao, Yuan Xin Chen, Ru Yu Li
  • Publication number: 20240373069
    Abstract: A method for video coding is provided. The method includes: setting, by an encoder, a first syntax element in a picture parameter set (PPS) specifying whether a picture corresponding to the PPS comprises more than one network abstraction layer (NAL) units and whether the more than one NAL units have a same NAL unit type; setting, by the encoder, a second syntax element in a picture header (PH) specifying whether the picture corresponding to the PH is an intra random access point (IRAP) picture or a gradual decoding refresh (GDR) picture, wherein a value of the first syntax element is set based on a value of the second syntax element being 1; and forming, by the encoder, a bitstream with the first syntax element and the second syntax element.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Applicant: BEIJING DAJIA INTERNET INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Xiaoyu XIU, Yi-wen CHEN, Tsung-Chuan MA, Hong-Jheng JHU, Wei CHEN, Xianglin WANG, Bing YU
  • Publication number: 20240371904
    Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Wei Chuang Wu, Dun-Nian Yaung, Feng-Chi Hung, Jen-Cheng Liu, Jhy-Jyi Sze, Keng-Yu Chou, Yen-Ting Chiang, Ming-Hsien Yang, Chun-Yuan Chen
  • Publication number: 20240370631
    Abstract: A system including computer readable storage media including executable instructions and one or more processors configured to execute the executable instructions to obtain a schematic netlist and a performance specification for an integrated circuit, determine electrical constraints for nets in the schematic netlist based on the performance specification, determine physical constraints from the electrical constraints, rout the nets in the schematic netlist based on the electrical constraints and the physical constraints, and provide a data file of a layout.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Hsien Yu Tseng, Guan-Ruei Lu, Wei-Ming Chen, Chih.Chi. Hsiao
  • Publication number: 20240371840
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
  • Publication number: 20240371314
    Abstract: The present disclosure related to a common cathode micro led display with a driving circuit, a ground end, a plurality of LED units and a plurality switch units. The driving circuit connected to a plurality of transmission wires. One end of the plurality of LED units or one end of the plurality switch units is electronically connected to the plurality of transmission wires. The ground end is configured with a plurality of scan lines. Free ends formed by the plurality of LED units and the plurality switch units connected in series connect to the scan lines. A plurality of vertical conducted groups or a plurality of horizontal conducted groups are formed according to the switch units. A control unit is configured to drive the plurality of vertical conduction groups or the plurality of horizontal conduction groups. Therefore, the object to avoid voltage drop caused by the drive current is achieved.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 7, 2024
    Applicant: GIANTPLUS TECHNOLOGY CO., LTD.
    Inventor: Wei-Yu CHEN
  • Patent number: 12134690
    Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Photoresist layer is selectively exposed to radiation, and selectively exposed photoresist layer developed. Photoresist composition includes photoactive compound, crosslinker, copolymer.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: November 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Hao Chen, Wei-Han Lai, Ching-Yu Chang
  • Patent number: 12136570
    Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: November 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Wei-Yen Woon, Cheng-Ming Lin, Han-Yu Lin, Szu-Hua Chen, Jhih-Rong Huang, Tzer-Min Shen
  • Patent number: 12137548
    Abstract: A memory device includes active regions and gate structures, each of the gate structures is electrically coupled to a first portion of a corresponding active region of the active regions. The memory device includes contact-to-transistor-component structures (MD structures), each of the MD structures is over a second portion of a corresponding active region, and a first MD structure is between adjacent gate structures. The memory device includes via-to-gate/MD (VGD) structures, each of the VGD structures is over to a corresponding gate electrode and MD structure. The memory device includes conductive segments, each of the conductive segments is over and electrically coupled to a corresponding VGD structure. The memory device includes buried contact-to-transistor-component structures (BVD) structures, each of the BVD structures is under a third portion of a corresponding active region.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: November 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen, Wei-Chang Zhao, Yi-Hsin Nien
  • Publication number: 20240363676
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The magnetic element has multiple sub-layers, and each sub-layer is wider than another sub-layer above it. The semiconductor device structure also includes an isolation layer extending exceeding edges the magnetic element, and the isolation layer contains a polymer material. The semiconductor device structure further includes a conductive line over the isolation layer and extending exceeding the edges of the magnetic element.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Cheng CHEN, Wei-Li HUANG, Chun-Yi WU, Kuang-Yi WU, Hon-Lin HUANG, Chih-Hung SU, Chin-Yu KU, Chen-Shien CHEN
  • Publication number: 20240363426
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate, at least two gate structures disposed over the substrate, each of the at least two gate structures including a gate electrode and a spacer disposed along sidewalls of the gate electrode, wherein the spacer includes a refill portion and a bottom portion, the refill portion of the spacer has a funnel shape such that a top surface of the refill portion of the spacer is larger than a bottom surface of the refill portion of the spacer, and a source/drain contact disposed over the substrate and between the spacers of the at least two gate structures.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Cheng-Yu Yang, Yen-Ting Chen, Wei-Yang Lee, Fu-Kai Yang, Yen-Ming Chen
  • Publication number: 20240364885
    Abstract: An electronic apparatus performs a method of coding video data. The method comprises: receiving, from the bitstream, syntax elements associated with a coding unit, wherein the syntax elements include a first coded block flag (CBF) for residual samples of a first chroma component, a second CBF for residual samples of a second chroma component, and a third syntax element indicating whether adaptive color transform (ACT) is applied to the coding unit; determining whether to perform the chroma residual scaling to the residual samples of the chroma components according to the first CBF, the second CBF, and the third syntax element; in accordance with a determination to perform the chroma residual scaling to the residual samples of the first and second chroma components, scaling the residual samples of the at least one of the first and second chroma components based on a corresponding scaling parameter.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Xiaoyu XIU, Yi-Wen CHEN, Tsung-Chuan MA, Hong-Jheng JHU, Wei CHEN, Che-Wei KUO, Xianglin WANG, Bing YU
  • Publication number: 20240363576
    Abstract: A semiconductor package structure includes a semiconductor die encapsulated in a molding compound, a redistribution structure over the semiconductor die and the molding compound, a surface device over and electrically connected to the redistribution structure, a first connector over and electrically connected to the redistribution structure, a second connector between the surface device and the redistribution structure, a trench in the redistribution structure and laterally surrounding the surface device in a top view of the semiconductor package structure, and an underfill. The second connector electrically connects the surface device to the redistribution structure. The underfill surrounds the second connector. The underfill include a first portion and a second portion. The first portion of the underfill is located between the surface device and the redistribution structure and laterally surrounding the second connector, and the second portion of the underfill is disposed in the trench.
    Type: Application
    Filed: April 25, 2023
    Publication date: October 31, 2024
    Inventors: WEI-YU CHOU, YANG-CHE CHEN, YI-LUN YANG, TING-YUAN HUANG, HSIANG-TAI LU
  • Publication number: 20240364884
    Abstract: An electronic apparatus performs a method of coding video data. The method comprises: receiving, from the bitstream, syntax elements associated with a coding unit, wherein the syntax elements include a first coded block flag (CBF) for residual samples of a first chroma component, a second CBF for residual samples of a second chroma component, and a third syntax element indicating whether adaptive color transform (ACT) is applied to the coding unit; determining whether to perform the chroma residual scaling to the residual samples of the chroma components according to the first CBF, the second CBF, and the third syntax element; in accordance with a determination to perform the chroma residual scaling to the residual samples of the first and second chroma components, scaling the residual samples of the at least one of the first and second chroma components based on a corresponding scaling parameter.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Xiaoyu XIU, Yi-Wen CHEN, Tsung-Chuan MA, Hong-Jheng JHU, Wei CHEN, Che-Wei KUO, Xianglin WANG, Bing YU
  • Publication number: 20240363388
    Abstract: An adhesion film with a plurality of semiconductor packages thereupon may be positioned on a pedestal including an enclosure and having a perforated top surface, a first support ring located at a periphery of the perforated top surface, and a second support ring laterally surrounding the first support ring. A first semiconductor package overlaps segments of the first support ring at a plurality of overlap areas in a top-down view, and does not contact the second support ring in the top-down view. A vacuum suction may be applied to a volume within the enclosure and to a gap which is vertically bounded by a bottom surface of the adhesion film and is laterally bounded by the first support ring while holding the first semiconductor package stationary. A portion of the adhesion film underlying the first semiconductor package is peeled off a bottom surface of the first semiconductor package.
    Type: Application
    Filed: April 26, 2023
    Publication date: October 31, 2024
    Inventors: Hsin Liang Chen, Ching-Hua Hsieh, Hsiu-Jen Lin, Hsuan-Ting Kuo, Wei-Yu Chen, Cheng-Shiuan Wong
  • Publication number: 20240363421
    Abstract: The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Yu LIN, Szu-Hua Chen, Kuan-Kan Hu, Kenichi Sano, Po-Cheng Wang, Wei-Yen Woon, Pinyen Lin, Che Chi Shih
  • Publication number: 20240361609
    Abstract: Disclosed is a method to fabricate a multifunctional collimator structure In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; and a plurality of via holes, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, wherein the substrate has a bulk impurity doping concentration equal to or greater than 1×1019 per cubic centimeter (cm?3) and a first thickness, and wherein the bulk impurity doping concentration and the first thickness of the substrate are configured so as to allow the optical collimator to filter light in a range of wavelengths.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Hsin-Yu CHEN, Chun-Peng LI, Chia-Chun HUNG, Ching-Hsiang HU, Wei-Ding WU, Jui-Chun WENG, Ji-Hong CHIANG, Yen Chiang LIU, Jiun-Jie CHIOU, Li-Yang TU, Jia-Syuan LI, You-Cheng JHANG, Shin-Hua CHEN, Lavanya SANAGAVARAPU, Han-Zong PAN, Hsi-Cheng HSU
  • Publication number: 20240364886
    Abstract: An electronic apparatus performs a method of coding video data. The method comprises: receiving, from the bitstream, syntax elements associated with a coding unit, wherein the syntax elements include a first coded block flag (CBF) for residual samples of a first chroma component, a second CBF for residual samples of a second chroma component, and a third syntax element indicating whether adaptive color transform (ACT) is applied to the coding unit; determining whether to perform the chroma residual scaling to the residual samples of the chroma components according to the first CBF, the second CBF, and the third syntax element; in accordance with a determination to perform the chroma residual scaling to the residual samples of the first and second chroma components, scaling the residual samples of the at least one of the first and second chroma components based on a corresponding scaling parameter.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Xiaoyu XIU, Yi-Wen CHEN, Tsung-Chuan MA, Hong-Jheng JHU, Wei CHEN, Che-Wei KUO, Xianglin WANG, Bing YU
  • Patent number: 12133323
    Abstract: A transmission device for suppressing the glass-fiber effect includes a circuit board and a transmission line. The circuit board includes a plurality of glass fibers, so as to define a fiber pitch. The transmission line is disposed on the circuit board. The transmission line includes a plurality of non-parallel segments. Each of the non-parallel segments of the transmission line has an offset distance with respect to a reference line. The offset distance is longer than or equal to a half of the fiber pitch.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: October 29, 2024
    Assignees: UNIMICRON TECHNOLOGY CORP., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chin-Hsun Wang, Ruey-Beei Wu, Ching-Sheng Chen, Chun-Jui Huang, Wei-Yu Liao, Chi-Min Chang
  • Publication number: 20240352187
    Abstract: A polymer, which is a composition of a battery, includes a polyester. The polyester is polymerized by at least two monomers, wherein each of the at least two monomers is selected from a group consisting of a carbonate ester and a polyol. The polyester can further include an end-capped polycarbonate ester, and the end-capped polycarbonate ester includes an inert group on an end thereof.
    Type: Application
    Filed: April 11, 2024
    Publication date: October 24, 2024
    Inventors: Wei-Yuan CHEN, Po-Tsun CHEN, Rih-Sian CHEN, Yi-Rou LU, Chia-Ying LI, Cheng-Yu TSAI, Chun-Hung TENG