Patents by Inventor Wei Yu Ma
Wei Yu Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10043767Abstract: A method is disclosed that includes the operations outlined below. A plurality of dummy conductive cells that provide different densities are formed in a plurality of empty areas in a plurality of metal layers of a semiconductor device according to overlap conditions of the empty areas between each pair of neighboring metal layers.Type: GrantFiled: October 24, 2013Date of Patent: August 7, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Wei-Yu Ma, Hui-Mei Chou, Kuo-Ji Chen
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Publication number: 20180151492Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.Type: ApplicationFiled: January 26, 2018Publication date: May 31, 2018Inventors: Wei-Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
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Patent number: 9893010Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.Type: GrantFiled: July 20, 2016Date of Patent: February 13, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
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Publication number: 20170207295Abstract: A method includes determining an active region pattern density of a first region of an integrated circuit layout based on a total area of each active region in the first region and an area of the first region. The method includes determining an active region pattern density of a second region of the integrated circuit layout based on a total area of each active region in the second region and an area of the second region. The method includes determining an active region pattern density gradient between the first region to the second region. The method includes determining whether the first region or the second region includes a resistive device. The method includes modifying a portion of the resistive device to include an incremental resistor in response to the first region or the second region including the resistive device.Type: ApplicationFiled: April 4, 2017Publication date: July 20, 2017Inventors: Wei-Yu MA, Chia-Hui CHEN, Yi-Ting WANG
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Patent number: 9640605Abstract: A semiconductor device includes a first semiconductor structure having a first active region pattern density. The semiconductor device further includes a second semiconductor structure having a second active region pattern density, wherein the second semiconductor structure comprises a first resistive element. The semiconductor device further includes a third semiconductor structure having a third active region pattern density, wherein the third semiconductor structure includes a second resistive element. The second semiconductor structure is adjacent to the first semiconductor structure and adjacent to the third semiconductor structure. The first semiconductor structure, the second semiconductor structure and the third semiconductor structure do not overlap.Type: GrantFiled: April 23, 2015Date of Patent: May 2, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Yu Ma, Chia-Hui Chen, Yi-Ting Wang
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Publication number: 20160329280Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.Type: ApplicationFiled: July 20, 2016Publication date: November 10, 2016Inventors: Wei-Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
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Patent number: 9478533Abstract: An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor.Type: GrantFiled: May 18, 2015Date of Patent: October 25, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei Yu Ma, Bo-Ting Chen, Ting Yu Chen, Kuo-Ji Chen, Li-Chun Tien
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Patent number: 9472545Abstract: One or more semiconductor arrangements having a stacked configuration and electrostatic discharge (ESD) protection are provided. The semiconductor arrangements include a first substrate, a second substrate, an ESD pad, an ESD device and a first interlayer via connecting the first substrate and the second substrate. The first substrate includes a first PMOS device and a first device and the second substrate includes a first NMOS device and a second device. Alternatively, the first substrate includes a first PMOS device and a first NMOS device and the second substrate includes a first device and a second device.Type: GrantFiled: January 31, 2014Date of Patent: October 18, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chia-Hui Chen, Wei Yu Ma, Kuo-Ji Chen
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Publication number: 20160293689Abstract: A semiconductor device includes a first semiconductor structure having a first active region pattern density. The semiconductor device further includes a second semiconductor structure having a second active region pattern density, wherein the second semiconductor structure comprises a first resistive element. The semiconductor device further includes a third semiconductor structure having a third active region pattern density, wherein the third semiconductor structure includes a second resistive element. The second semiconductor structure is adjacent to the first semiconductor structure and adjacent to the third semiconductor structure. The first semiconductor structure, the second semiconductor structure and the third semiconductor structure do not overlap.Type: ApplicationFiled: April 23, 2015Publication date: October 6, 2016Inventors: Wei-Yu MA, Chia-Hui CHEN, Yi-Ting WANG
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Patent number: 9406607Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.Type: GrantFiled: October 21, 2013Date of Patent: August 2, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
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Patent number: 9293606Abstract: A seal ring for semiconductor devices is provided with embedded decoupling capacitors. The seal ring peripherally surrounds an integrated circuit chip in a seal ring area. The at least one embedded decoupling capacitor may include MOS capacitors, varactors, MOM capacitors and interdigitized capacitors with multiple capacitor plates coupled together. The opposed capacitor plates are coupled to different potentials and may advantageously be coupled to Vdd and Vss.Type: GrantFiled: November 15, 2011Date of Patent: March 22, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Ji Chen, Wei Yu Ma, Ta-Pen Guo, Hsien-Wei Chen, Hao-Yi Tsai
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Patent number: 9172244Abstract: A circuit with an electro-static discharge clamp coupled to a first power source and second power source. The electro-static discharge clamp includes an NMOS stack and an electro-static discharge detector. The NMOS stack has a first NMOS transistor with a first gate node and a second NMOS transistor with a second gate node. The electro-static discharge detector is configured to control the NMOS stack, and may include three switches. A first switch is configured to switch the first gate node to the second power source. A second switch is configured to switch the first gate node to the second gate node. A third switch is configured to switch the first gate node to the ground.Type: GrantFiled: May 30, 2014Date of Patent: October 27, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Wei Yu Ma
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Publication number: 20150249080Abstract: An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor.Type: ApplicationFiled: May 18, 2015Publication date: September 3, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei Yu MA, Bo-Ting CHEN, Ting Yu CHEN, Kuo-Ji CHEN, Li-Chun TIEN
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Patent number: 9124086Abstract: Among other things, one or more techniques and/or systems for providing failsafe electrostatic discharge (ESD) protection are provided. In one embodiment, ESD protection is provided by connecting a voltage fail safe (VFS) supply voltage to an NWELL circuit interface (e.g., of a PMOS transistor) and connecting PAD to at least one of VFS or the NWELL circuit interface. To this end, circuitry to be protected from ESD (e.g., circuitry operably connected to PAD) is provided with failsafe ESD protection (e.g., such that a non-snapback NMOS device may be utilized to discharge ESD current, where a non-snapback NMOS generally consumes less semiconductor real estate and is less complex to produce as compared to a snapback NMOS), for example. In this manner, failsafe ESD protection is efficiently provided.Type: GrantFiled: July 25, 2012Date of Patent: September 1, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Wei Yu Ma, Kuo-Ji Chen
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Patent number: 9117677Abstract: The present application discloses a semiconductor integrated circuit including a substrate having electrical devices formed thereon, a local interconnection layer formed over the substrate, and a global interconnection layer formed over the local interconnection layer. The local interconnection layer has a first set of conductive structures arranged to electrically connect within the individual electrical devices, among one of the electrical devices and its adjacent electrical devices, or vertically between the devices and the global interconnection layer. At least one of the first set of conductive structures is configured to have a resistance value greater than 50 ohms. The global interconnection layer has a second set of conductive structures arranged to electrically interconnect the electrical devices via the first set conductive structures.Type: GrantFiled: October 13, 2011Date of Patent: August 25, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei Yu Ma, Kuo-Ji Chen, Fang-Tsun Chu, Ta-Pen Guo
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Publication number: 20150221636Abstract: One or more semiconductor arrangements having a stacked configuration and electrostatic discharge (ESD) protection are provided. The semiconductor arrangements include a first substrate, a second substrate, an ESD pad, an ESD device and a first interlayer via connecting the first substrate and the second substrate. The first substrate includes a first PMOS device and a first device and the second substrate includes a first NMOS device and a second device. Alternatively, the first substrate includes a first PMOS device and a first NMOS device and the second substrate includes a first device and a second device.Type: ApplicationFiled: January 31, 2014Publication date: August 6, 2015Inventors: Chia-Hui Chen, Wei Yu Ma, Kuo-Ji Chen
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Publication number: 20150214211Abstract: An integrated circuit includes two or more substrates stacked one over another and a first set of electrical components on one or more of the two or more substrates. The two or more substrates include a first substrate having a first predetermined doping type and a second substrate having the first predetermined doping type. The first set of electrical components is configured to form a first circuit. The integrated circuit further includes a first ground reference rail electrically connected to the first circuit, a first common ground reference rail, and a first ESD conduction element electrically connected between the first ground reference rail and the first common ground reference rail. The first ESD conduction element includes a first diode on the first substrate and a second diode on the second substrate. The first diode and the second diode are electrically connected in parallel and have opposite polarities.Type: ApplicationFiled: January 30, 2014Publication date: July 30, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei Yu MA, Chia-Hui CHEN, Kuo-Ji CHEN
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Patent number: 9035393Abstract: An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor.Type: GrantFiled: February 28, 2013Date of Patent: May 19, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei Yu Ma, Bo-Ting Chen, Ting Yu Chen, Kuo-Ji Chen, Li-Chun Tien
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Publication number: 20150115419Abstract: A method is disclosed that includes the operations outlined below. A plurality of dummy conductive cells that provide different densities are formed in a plurality of empty areas in a plurality of metal layers of a semiconductor device according to overlap conditions of the empty areas between each pair of neighboring metal layers.Type: ApplicationFiled: October 24, 2013Publication date: April 30, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Yu MA, Hui-Mei CHOU, Kuo-Ji CHEN
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Publication number: 20140210014Abstract: An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor.Type: ApplicationFiled: February 28, 2013Publication date: July 31, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei Yu MA, Bo-Ting CHEN, Ting Yu CHEN, Kuo-Ji CHEN, Li-Chun TIEN