Patents by Inventor Wei-Yuan Cheng

Wei-Yuan Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10950588
    Abstract: A chip package structure including a redistribution structure layer, at least one chip, and an encapsulant is provided. The redistribution structure layer includes at least one redistribution circuit, at least one transistor electrically connected to the redistribution circuit, and a plurality of conductive vias electrically connected to the redistribution circuit and the transistor. The chip is disposed on the redistribution structure layer and electrically connected to the redistribution structure layer. The encapsulant is disposed on the redistribution structure layer and at least encapsulates the chip. A manufacturing method of a chip package structure is also provided.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: March 16, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Hung Yu, Tai-Jui Wang, Chieh-Wei Feng, Wei-Yuan Cheng
  • Patent number: 10709956
    Abstract: A multiplayer sports formation arrangement prompting method adapted to monitor, by a computing device, a formation of a plurality of athletes participating in a multiplayer sport to prompt each of the athletes to adjust a position is provided, in which at least two wind sensors and a positioning device are disposed on or around each of the athletes.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: July 14, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Min-Hsiung Liang, Yen-Ting Wu, Wei-Yuan Cheng, Ming-Huan Yang
  • Publication number: 20200211984
    Abstract: An electronic device package structure and a manufacturing method thereof are provided. The electronic device package structure includes a first electronic device layer, a second electronic device layer, and a filling layer disposed between the first electronic device layer and the second electronic device layer, wherein the Young's modulus of the second electronic device layer is less than or equal to the Young's modulus of the first electronic device layer, and the Young's modulus of the filling layer is less than the Young's modulus of the second electronic device layer, and the ratio of the Young's modulus of the first electronic device layer to the Young's modulus of the filling layer is 10 to 1900 and the ratio of the Young's modulus of the second electronic device layer to the Young's modulus of the filling layer is 7.6 to 1300.
    Type: Application
    Filed: May 7, 2019
    Publication date: July 2, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Jui-Chang Chuang, Chen-Tsai Yang, Wei-Yuan Cheng
  • Publication number: 20200185344
    Abstract: A chip package structure includes a redistribution circuit layer, at least one chip and an encapsulation material. The redistribution circuit layer includes at least one transistor. The chip is arranged on the redistribution circuit layer and is electrically connected to the redistribution circuit layer. The encapsulation material is arranged on the redistribution circuit layer and covers the at least one chip. When the chip package structure includes one or more chips, a position of the chip is taken as a reference for arrangement of a position of the at least one transistor.
    Type: Application
    Filed: July 2, 2019
    Publication date: June 11, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Wei-Yuan Cheng, Chen-Tsai Yang
  • Patent number: 10573587
    Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, an under bump supporting layer, an attachment layer and solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface and a patterned circuit layer disposed on the first surface, wherein an outer surface of the patterned circuit layer and the first surface are coplanar. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface to encapsulate the chip. The under bump supporting layer is disposed on the first surface and includes openings for exposing the outer surface. The attachment layer covers the inner surface of each opening and the exposed portion of the patterned circuit layer. The solder balls are disposed in the openings respectively and electrically connected to the patterned circuit layer.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: February 25, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Shu-Wei Kuo, Chun-Yi Cheng, Wei-Yuan Cheng
  • Patent number: 10522438
    Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, a plurality of under ball release layers, and a plurality of solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface, and a patterned circuit layer, wherein the patterned circuit layer includes a plurality of pads protruding from the first surface. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface and encapsulates the chip. The under ball release layers cover the pads respectively. The solder balls are disposed on the under ball release layers and electrically connected to the pads.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: December 31, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Chun-Yi Cheng, Wei-Yuan Cheng, Shu-Wei Kuo, Yu-Jhen Yang
  • Publication number: 20190341373
    Abstract: A chip package structure including a redistribution structure layer, at least one chip, and an encapsulant is provided. The redistribution structure layer includes at least one redistribution circuit, at least one transistor electrically connected to the redistribution circuit, and a plurality of conductive vias electrically connected to the redistribution circuit and the transistor. The chip is disposed on the redistribution structure layer and electrically connected to the redistribution structure layer. The encapsulant is disposed on the redistribution structure layer and at least encapsulates the chip. A manufacturing method of a chip package structure is also provided.
    Type: Application
    Filed: July 5, 2018
    Publication date: November 7, 2019
    Applicant: Industrial Technology Research Institute
    Inventors: Cheng-Hung Yu, Tai-Jui Wang, Chieh-Wei Feng, Wei-Yuan Cheng
  • Patent number: 10461035
    Abstract: A semiconductor package structure includes a redistribution structure, a chip, an upper dielectric layer, a plurality of conductive members and an encapsulation layer. The redistribution structure includes a redistribution layer and a first dielectric layer disposed on the redistribution layer. The upper dielectric layer is disposed between the chip and the first dielectric layer of the redistribution structure, wherein the upper dielectric layer and the first dielectric layer are organic materials. A plurality of conductive members is disposed between the redistribution layer and the chip. Each conductive member has a first end adjacent to the chip and a second end adjacent to the redistribution structure, wherein the first end of said each conductive member contacts with the upper dielectric layer and the second end of said each conductive member contacts with the first dielectric layer.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 29, 2019
    Assignees: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Shu-Wei Kuo, Wei-Yuan Cheng, Chen-Tsai Yang, Jie-Mo Lin
  • Patent number: 10366965
    Abstract: A chip bonding apparatus for bonding a chip and a redistribution structure with each other is provided. The chip bonding apparatus includes a pick and place module and an alignment module. The pick and place module is suitable for picking up and placing the chip. The alignment module is movably connected to the pick and place module. The alignment module includes at least one alignment protrusion, wherein the at least one alignment protrusion extends toward at least one alignment socket included in the redistribution structure. Furthermore, a chip bonding method and a chip package structure are provided.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: July 30, 2019
    Assignees: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Shu-Wei Kuo, Wei-Yuan Cheng, Shau-Fei Cheng
  • Publication number: 20190131271
    Abstract: A chip bonding apparatus for bonding a chip and a redistribution structure with each other is provided. The chip bonding apparatus includes a pick and place module and an alignment module. The pick and place module is suitable for picking up and placing the chip. The alignment module is movably connected to the pick and place module. The alignment module includes at least one alignment protrusion, wherein the at least one alignment protrusion extends toward at least one alignment socket included in the redistribution structure. Furthermore, a chip bonding method and a chip package structure are provided.
    Type: Application
    Filed: December 28, 2017
    Publication date: May 2, 2019
    Applicants: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Shu-Wei Kuo, Wei-Yuan Cheng, Shau-Fei Cheng
  • Patent number: 10249567
    Abstract: A redistribution layer structure of the semiconductor package includes a dielectric layer having a thickness, at least one upper conductive wire disposed on a first surface of the dielectric layer, at least one lower conductive wire disposed on a second surface of the dielectric layer, and vias penetrating the dielectric layer and connecting the at least one upper conductive wire and the at least one lower conductive wire. Each via has a cross-section at one upper conductive wire. The cross-section has a third width. The ratio of the third width to the thickness of the dielectric layer is less than or equal to 1. The ratio of the pitch between every two adjacent vias to the third width is greater than or equal to 0.5.
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: April 2, 2019
    Assignees: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Jie-Mo Lin, Shu-Wei Kuo, Wei-Yuan Cheng, Chen-Tsai Yang
  • Publication number: 20190088600
    Abstract: A semiconductor package structure includes a redistribution structure, a chip, an upper dielectric layer, a plurality of conductive members and an encapsulation layer. The redistribution structure includes a redistribution layer and a first dielectric layer disposed on the redistribution layer. The upper dielectric layer is disposed between the chip and the first dielectric layer of the redistribution structure, wherein the upper dielectric layer and the first dielectric layer are organic materials. A plurality of conductive members is disposed between the redistribution layer and the chip. Each conductive member has a first end adjacent to the chip and a second end adjacent to the redistribution structure, wherein the first end of said each conductive member contacts with the upper dielectric layer and the second end of said each conductive member contacts with the first dielectric layer.
    Type: Application
    Filed: December 20, 2017
    Publication date: March 21, 2019
    Applicants: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Shu-Wei Kuo, Wei-Yuan Cheng, Chen-Tsai Yang, Jie-Mo Lin
  • Publication number: 20190057934
    Abstract: A redistribution layer structure of the semiconductor package includes a dielectric layer having a thickness, at least one upper conductive wire disposed on a first surface of the dielectric layer, at least one lower conductive wire disposed on a second surface of the dielectric layer, and vias penetrating the dielectric layer and connecting the at least one upper conductive wire and the at least one lower conductive wire. Each via has a cross-section at one upper conductive wire. The cross-section has a third width. The ratio of the third width to the thickness of the dielectric layer is less than or equal to 1. The ratio of the pitch between every two adjacent vias to the third width is greater than or equal to 0.5.
    Type: Application
    Filed: December 25, 2017
    Publication date: February 21, 2019
    Applicants: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Jie-Mo Lin, Shu-Wei Kuo, Wei-Yuan Cheng, Chen-Tsai Yang
  • Publication number: 20180294202
    Abstract: A chip package structure and a manufacturing method thereof are provided. The chip package structure includes a frame disposed around a chip, a filling material filled in the space between the chip and the frame, and a protection layer covering the chip, the frame, and the filling material. The Young's modulus of the filling material is respectively smaller than the Young's modulus of the chip, the Young's modulus of the frame, and the Young's modulus of the protection layer.
    Type: Application
    Filed: December 28, 2017
    Publication date: October 11, 2018
    Applicants: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Wei-Yuan Cheng, Cheng-Chung Lee, Shau-Fei Cheng, Wen-Lung Chen
  • Publication number: 20180122694
    Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, a plurality of under ball release layers, and a plurality of solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface, and a patterned circuit layer, wherein the patterned circuit layer includes a plurality of pads protruding from the first surface. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface and encapsulates the chip. The under ball release layers cover the pads respectively. The solder balls are disposed on the under ball release layers and electrically connected to the pads.
    Type: Application
    Filed: May 16, 2017
    Publication date: May 3, 2018
    Applicant: Industrial Technology Research Institute
    Inventors: Chun-Yi Cheng, Wei-Yuan Cheng, Shu-Wei Kuo, Yu-Jhen Yang
  • Publication number: 20180122732
    Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, an under bump supporting layer, an attachment layer and solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface and a patterned circuit layer disposed on the first surface, wherein an outer surface of the patterned circuit layer and the first surface are coplanar. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface to encapsulate the chip. The under bump supporting layer is disposed on the first surface and includes openings for exposing the outer surface. The attachment layer covers the inner surface of each opening and the exposed portion of the patterned circuit layer. The solder balls are disposed in the openings respectively and electrically connected to the patterned circuit layer.
    Type: Application
    Filed: August 10, 2017
    Publication date: May 3, 2018
    Applicant: Industrial Technology Research Institute
    Inventors: Shu-Wei Kuo, Chun-Yi Cheng, Wei-Yuan Cheng
  • Publication number: 20170262129
    Abstract: According to an embodiment of the present disclosure, an electrical device may include a substrate, an electrical element, a first barrier structure and a gas barrier layer. The substrate includes an active region and a periphery region surrounding the active region. The electrical element is disposed in the active region. The first barrier structure is disposed in the periphery region and surrounds the electrical element, wherein the first barrier structure includes a first conductive layer. The gas barrier layer covers the electrical element and the first barrier structure.
    Type: Application
    Filed: August 12, 2016
    Publication date: September 14, 2017
    Applicant: Industrial Technology Research Institute
    Inventors: Wei-Yuan Cheng, Chih-Chia Chang, Ruo-Lan Chang, Pei-Pei Cheng, Chao-Wen Chen
  • Patent number: 9591746
    Abstract: According to embodiments of the disclosure, an electronic device package may include a wire layer and a rigid element. The wire layer includes a first surface and a second surface opposite to each other, and the second surface of the wire layer has at least one coarse structure. A portion of the second surface having the coarse structure has a greater roughness than another portion of the second surface. The rigid element is disposed on the first surface of the wire layer, wherein a stiffness of the rigid element is greater than a stiffness of the wire layer and a projection area of the coarse structure on the first surface of the wire layer overlaps an edge of the rigid element.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: March 7, 2017
    Assignee: Industrial Technology Research Institute
    Inventors: Wei-Yuan Cheng, Chen-Chu Tsai, Yuh-Zheng Lee
  • Patent number: 9547213
    Abstract: A display device including a first substrate, a second substrate, a display element layer, a non-transparent structure, an optical guiding structure and a reflective layer is disclosed. The second substrate is disposed opposite to the first substrate adjacent to a display surface of the display device. The display element layer is disposed between the first and the second substrates. The non-transparent structure, located between the optical guiding structure and the display element layer, defines at least one opening of the display device. The optical guiding structure corresponds to the one opening. The optical guiding structure includes a plurality of insulating structures each having a first surface adjacent to the non-transparent structure and side surfaces connected to the first surface. The reflective layer is disposed on the side surfaces. The ambient light entering via the second substrate is reflected by the reflective layer and exists via the opening.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: January 17, 2017
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Kuo-Chang Lee, Kuo-Lung Lo, Wei-Yuan Cheng
  • Patent number: 9529452
    Abstract: A touch input device includes a touch end, a sensing module, and a receiving module. The sensing module includes a sensing unit and a signal operation unit. The sensing unit detects a relative angle between the touch end and a display touch surface to generate a motion signal. The signal operation unit is coupled with the sensing unit and generates a result signal according to the motion signal. The receiving module includes a receiving end and a demodulator unit. The receiving end receives the result signal; the demodulator is coupled with the receiving end, wherein the receiving end transmits the result signal to the demodulator unit, and the demodulator unit generates a function signal according to the result signal.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: December 27, 2016
    Assignee: Raydium Semiconductor Corporation
    Inventors: Te-Chang Lin, Chien-Kuo Wang, Chia-Hsiu Lin, Ya-Ling Lu, Yi-Ming Chen, Wei-Yuan Cheng, Yu-Sheng Yeh