Patents by Inventor Wei-Yuan Lu
Wei-Yuan Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9299838Abstract: A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET). The Method includes performing an implantation to form a pre-amorphization implantation (PAI) region adjacent to a gate electrode of the MOSFET, forming a strained capping layer over the PAI region, and performing an annealing on the strained capping layer and the PAI region to form a dislocation plane. The dislocation plane is formed as a result of the annealing, with a tilt angle of the dislocation plane being smaller than about 65 degrees.Type: GrantFiled: August 8, 2014Date of Patent: March 29, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Wei-Yuan Lu
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Patent number: 9299803Abstract: Provided is a method of forming a semiconductor device. The method includes providing a substrate having n-type doped source/drain features; depositing a flowable dielectric material layer over the substrate; and performing a wet annealing process to the flowable dielectric material layer. The wet annealing process includes a first portion performed at a temperature below 600 degrees Celsius (° C.) and a second portion performed at temperatures above 850° C. wherein the second portion is performed for a shorter duration than the first portion. In embodiments, the second portion has a spike temperature ramp profile with a peak temperature ranging from about 900° C. to about 1,050° C. and a spike duration ranging from about 0.7 seconds to about 10 seconds. The wet annealing process satisfies thermal budget for converting the flowable dielectric material layer to a dense oxide layer while maintaining tensile strain in an n-channel between the doped source/drain features.Type: GrantFiled: July 16, 2014Date of Patent: March 29, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Hsiung Tsai, Wei-Yuan Lu
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Patent number: 9293534Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.Type: GrantFiled: March 21, 2014Date of Patent: March 22, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Wei-Yuan Lu, Chien-Tai Chan, Wei-Yang Lee, Da-Wen Lin
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Publication number: 20160027644Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes providing a substrate having a fin extending from the substrate. An in-situ doped layer is formed on the fin. By way of example, the in-situ doped layer may include an in-situ doped well region formed by an epitaxial growth process. In some examples, the in-situ doped well region includes an N-well or a P-well region. After formation of the in-situ doped layer on the fin, an undoped layer is formed on the in-situ doped layer, and a gate stack is formed over the undoped layer. The undoped layer may include an undoped channel region formed by an epitaxial growth process. In various examples, a source region and a drain region are formed adjacent to and on either side of the undoped channel region.Type: ApplicationFiled: July 24, 2014Publication date: January 28, 2016Inventors: Chun Hsiung Tsai, Wei-Yuan Lu
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Publication number: 20160020300Abstract: Provided is a method of forming a semiconductor device. The method includes providing a substrate having n-type doped source/drain features; depositing a flowable dielectric material layer over the substrate; and performing a wet annealing process to the flowable dielectric material layer. The wet annealing process includes a first portion performed at a temperature below 600 degrees Celsius (° C.) and a second portion performed at temperatures above 850° C. wherein the second portion is performed for a shorter duration than the first portion. In embodiments, the second portion has a spike temperature ramp profile with a peak temperature ranging from about 900° C. to about 1,050° C. and a spike duration ranging from about 0.7 seconds to about 10 seconds. The wet annealing process satisfies thermal budget for converting the flowable dielectric material layer to a dense oxide layer while maintaining tensile strain in an n-channel between the doped source/drain features.Type: ApplicationFiled: July 16, 2014Publication date: January 21, 2016Inventors: Chun Hsiung Tsai, Wei-Yuan Lu
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Publication number: 20150333076Abstract: A semiconductor device includes a dielectric layer on a substrate, a P-type transistor having a first gate stack embedded in the dielectric layer, and an N-type transistor having a second gate stack embedded in the dielectric layer. The first gate stack includes a first metal gate electrode, a first gate dielectric layer underlying the first metal gate electrode, and a first cap layer between the first gate dielectric layer and the first metal gate electrode. The second gate stack includes a second metal gate electrode, a second gate dielectric layer underlying the second metal gate electrode, and a second cap layer between the second gate dielectric layer and the second metal gate electrode. The first and second gate stacks are adjacent, and the first and second metal gate electrodes are separated from each other by the first and second cap layers.Type: ApplicationFiled: July 24, 2015Publication date: November 19, 2015Inventors: Wei-Yuan Lu, Kuan-Chung Chen, Chun-Fai Cheng
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Patent number: 9178063Abstract: A semiconductor device includes a gate structure over a substrate, a source region in the substrate, where the source region is adjacent to the gate structure. Additionally, the semiconductor device includes a drain region in the substrate, where the drain region is adjacent to the gate structure. Moreover, the semiconductor device includes a first dislocation in the substrate between the source region and the drain region. Furthermore, the semiconductor device includes a second dislocation in the substrate between the source region and the drain region, where the second dislocation is substantially parallel to the first dislocation.Type: GrantFiled: August 12, 2014Date of Patent: November 3, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Yuan Lu, Li-Ping Huang, Han-Ting Tsai, Wei-Ching Wang, Ming-Shuan Li, Hsueh-Jen Yang, Kuan-Chung Chen
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Publication number: 20150270342Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.Type: ApplicationFiled: March 21, 2014Publication date: September 24, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Wei-Yuan Lu, Chien-Tai Chan, Wei-Yang Lee, Da-Wen Lin
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Patent number: 9099346Abstract: A method for manufacturing a semiconductor device includes forming a first dummy gate on a substrate, performing a doping process to the substrate, thereby forming a source and a drain at sides of the first dummy gate, performing a first high temperature annealing to activate the source and drain, forming an inter-layer dielectric (ILD) material on the substrate, removing the first dummy gate to create an ILD trench, forming a first high-k dielectric layer within the ILD trench, forming a first dummy cap portion within the ILD trench over the first high-k dielectric layer, performing a second high-temperature annealing to reduce defects in the first high-k dielectric layer, and thereafter, replacing the first dummy cap portion with a first metal gate electrode.Type: GrantFiled: October 9, 2013Date of Patent: August 4, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yuan Lu, Kuan-Chung Chen, Chun-Fai Cheng
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Patent number: 8952459Abstract: A gate structure includes a gate dielectric over a substrate, and a gate electrode over the gate dielectric, wherein the gate dielectric contacts sidewalls of the gate electrode. The gate structure further includes a nitrogen-containing dielectric layer surrounding the gate electrode, and a contact etch stop layer (CESL) surrounding the nitrogen-containing dielectric layer. The gate structure further includes an interlayer dielectric layer surrounding the CESL and a lightly doped region in the substrate, the lightly doped region extends beyond an interface of the sidewalls of the gate electrode and the gate dielectric.Type: GrantFiled: August 20, 2013Date of Patent: February 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fung Ka Hing, Haiting Wang, Han-Ting Tsai, Chun-Fai Cheng, Wei-Yuan Lu, Hsien-Ching Lo, Kuan-Chung Chen
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Publication number: 20140346576Abstract: A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET). The Method includes performing an implantation to form a pre-amorphization implantation (PAI) region adjacent to a gate electrode of the MOSFET, forming a strained capping layer over the PAI region, and performing an annealing on the strained capping layer and the PAI region to form a dislocation plane. The dislocation plane is formed as a result of the annealing, with a tilt angle of the dislocation plane being smaller than about 65 degrees.Type: ApplicationFiled: August 8, 2014Publication date: November 27, 2014Inventor: Wei-Yuan Lu
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Publication number: 20140346614Abstract: A semiconductor device includes a gate structure over a substrate, a source region in the substrate, where the source region is adjacent to the gate structure. Additionally, the semiconductor device includes a drain region in the substrate, where the drain region is adjacent to the gate structure. Moreover, the semiconductor device includes a first dislocation in the substrate between the source region and the drain region. Furthermore, the semiconductor device includes a second dislocation in the substrate between the source region and the drain region, where the second dislocation is substantially parallel to the first dislocation.Type: ApplicationFiled: August 12, 2014Publication date: November 27, 2014Inventors: Wei-Yuan LU, Li-Ping HUANG, Han-Ting TSAI, Wei-Ching WANG, Ming-Shuan LI, Hsueh-Jen YANG, Kuan-Chung CHEN
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Publication number: 20140252468Abstract: Integrated circuit devices with field effect transistors have source and drain regions that include a first and a second layer. The first layer is formed below the plane of the channel region. The first layer includes doped silicon and carbon that has a crystal lattice structure that is smaller than that of silicon. The second layer is formed over the first layer and rises above the plane of the channel region. The second layer is formed by a material that includes doped epitaxially grown silicon. The second layer has an atomic fraction of carbon less than half that of the first layer. The first layer is formed to a depth at least 10 nm below the surface of the channel region. This structure facilitates the formation of source and drain extension areas that form very shallow junctions. The devices provide sources and drains that have low resistance while being comparatively resistant to short channel effects.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Wei-Yuan Lu, Lilly Su, Chun-Hung Huang, Chii-Horng Li, Jyh-Huei Chen
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Patent number: 8828817Abstract: A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film.Type: GrantFiled: January 23, 2012Date of Patent: September 9, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yuan Lu, Li-Ping Huang, Han-Ting Tsai, Wei-Ching Wang, Ming-Shuan Li, Hsueh-Jen Yang, Kuan-Chung Chen
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Patent number: 8815722Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. At least one silicon-containing layer is formed in source/drain (S/D) regions adjacent to sidewalls of the gate structure. An N-type doped silicon-containing layer is formed over the at least one silicon-containing layer. The N-type doped silicon-containing layer has an N-type dopant concentration higher than that of the at least one silicon-containing layer. The N-type doped silicon-containing layer is annealed so as to drive N-type dopants of the N-type doped silicon-containing layer to the S/D regions.Type: GrantFiled: October 17, 2011Date of Patent: August 26, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ka-Hing Fung, Wei-Yuan Lu, Han-Ting Tsai
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Patent number: 8809918Abstract: A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET), which includes forming a first dislocation plane adjacent to a gate electrode of the MOSFET, and forming a second dislocation plane adjacent to the gate electrode of the MOSFET. The first and the second dislocation planes are on a same side of the gate electrode, and extend into source/drain regions of the MOSFET.Type: GrantFiled: October 24, 2011Date of Patent: August 19, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yuan Lu, Li-Ping Huang, Han-Ting Tsai
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Patent number: 8754477Abstract: A method of fabricating and a semiconductor device with multiple dislocation structures is disclosed. The exemplary semiconductor device includes gate structure overlying a top surface of a semiconductor substrate and a first gate spacer disposed on a sidewall of the gate structure and overlying the top surface of the substrate. The semiconductor device further includes a crystallized semiconductor material overlying the top surface of the semiconductor substrate and adjacent to a sidewall of the first gate spacer. The semiconductor device further includes a second gate spacer disposed on the sidewall of the first gate spacer and overlying the crystallized semiconductor material. The semiconductor device further includes a first stressor region disposed in the semiconductor substrate and a second stressor region disposed in the semiconductor substrate and in the crystallized semiconductor material.Type: GrantFiled: October 20, 2011Date of Patent: June 17, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yuan Lu, Li-Ping Huang, Han-Ting Tsai, Wei-Ching Wang, Ming-Shuan Li, Hsueh-Jen Yang, Kuan-Chung Chen
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Publication number: 20140027843Abstract: A method for manufacturing a semiconductor device includes forming a first dummy gate on a substrate, performing a doping process to the substrate, thereby forming a source and a drain at sides of the first dummy gate, performing a first high temperature annealing to activate the source and drain, forming an inter-layer dielectric (ILD) material on the substrate, removing the first dummy gate to create an ILD trench, forming a first high-k dielectric layer within the ILD trench, forming a first dummy cap portion within the ILD trench over the first high-k dielectric layer, performing a second high-temperature annealing to reduce defects in the first high-k dielectric layer, and thereafter, replacing the first dummy cap portion with a first metal gate electrode.Type: ApplicationFiled: October 9, 2013Publication date: January 30, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yuan Lu, Kuan--Chung Chen, Chun-Fai Cheng
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Publication number: 20130334617Abstract: A gate structure includes a gate dielectric over a substrate, and a gate electrode over the gate dielectric, wherein the gate dielectric contacts sidewalls of the gate electrode. The gate structure further includes a nitrogen-containing dielectric layer surrounding the gate electrode, and a contact etch stop layer (CESL) surrounding the nitrogen-containing dielectric layer. The gate structure further includes an interlayer dielectric layer surrounding the CESL and a lightly doped region in the substrate, the lightly doped region extends beyond an interface of the sidewalls of the gate electrode and the gate dielectric.Type: ApplicationFiled: August 20, 2013Publication date: December 19, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fung Ka HING, Haiting WANG, Han-Ting TSAI, Chun-Fai CHENG, Wei-Yuan LU, Hsien-Ching LO, Kuan-Chung CHEN
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Patent number: 8580641Abstract: A method for manufacturing a semiconductor device includes forming a first dummy gate on a substrate, performing a doping process to the substrate, thereby forming a source and a drain at sides of the first dummy gate, performing a first high temperature annealing to activate the source and drain, forming an inter-layer dielectric (ILD) material on the substrate, removing the first dummy gate to create an ILD trench, forming a first high-k dielectric layer within the ILD trench, forming a first dummy cap portion within the ILD trench over the first high-k dielectric layer, performing a second high-temperature annealing to reduce defects in the first high-k dielectric layer, and thereafter, replacing the first dummy cap portion with a first metal gate electrode.Type: GrantFiled: July 26, 2011Date of Patent: November 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yuan Lu, Kuan-Chung Chen, Chun-Fai Cheng