Abstract: An embodiment of the present disclosure discloses a memory device. The memory device comprises a memory controller, a buffer and a memory array. The buffer is coupled to the memory controller or embedded in the memory controller. A storage space of the buffer is configured by the memory controller to include a plurality of groups. The memory array is coupled to the memory controller, and comprising a plurality of tiles. The groups are one-to-one corresponding to the tiles. Each of the groups is configured to store data to be written into the corresponding tile. The memory controller performs one or more write operations based on the groups.

Abstract: An in-memory computing method and apparatus, adapted for a processor to perform MAC operations on a memory, are provided. In the method, a format of binary data of weights is transformed from a floating-point format into a quantized format by truncating at least a portion of fraction bits of the binary data and calculating complements of remaining bits, and programming the transformed binary data into cells of the memory. A tuning procedure is performed by iteratively inputting binary data of input signals into the memory, integrating outputs of the memory, and adjusting the weights programmed to the cells based on the integrated outputs. The binary data of the weights is reshaped based on a probability of reducing bits with a value of one in the binary data of each weight. The tuning procedure is repeated until an end condition is met.

Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.

Abstract: An embodiment of the present disclosure discloses a memory device. The memory device comprises a memory controller, a buffer and a memory array. The buffer is coupled to the memory controller or embedded in the memory controller. A storage space of the buffer is configured by the memory controller to include a plurality of groups. The memory array is coupled to the memory controller, and comprising a plurality of tiles. The groups are one-to-one corresponding to the tiles. Each of the groups is configured to store data to be written into the corresponding tile. The memory controller performs one or more write operations based on the groups.

Abstract: A wireless device performs spatial reuse in a wireless local area network. When receiving a packet, the wireless device measures a received signal quality from a first portion of the packet, and determines a required signal quality for correctly decoding a payload of the packet based on information in a packet header. The wireless device compares the received signal quality with the required signal quality. If the received signal quality is lower than the required signal quality, the wireless device transmits a signal that overlaps in time and in frequency with a second portion of the packet. Alternatively, a wireless device may identify a Basic Service Set Identification (BSSID) of a received packet. If the BSSID indicates that the packet is an inter-BSS packet, the wireless device transmits a signal overlapping in time and in frequency with the packet before reception of a frame check sequence (FCS) in the packet.

Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. Each vector data is executed with a multiplying-operation, the MSB vector and the LSB vector of each vector data is executed with a first group-counting operation and a second group-counting operation respectively. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, the effective bit number stored by each memory unit is less than 2.

Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.

Abstract: Disclosed is a memory device and an operation method thereof. The operation method of memory device, comprising: programming a plurality of sub-matrices including at least one of non-zero element of a rearranged matrix to a plurality of operation units of the memory device; and programming a mapping table into a working memory of a memory device. The rearranged matrix is generated by rearrange a plurality of columns and a plurality of rows of an original matrix according to the positions of a plurality of non-zero elements of the original matrix. The mapping table comprises a correspondence of row indexes between the original matrix and the rearranged matrix, a correspondence of column indexes between the original matrix and the rearranged matrix and a correspondence between the sub-matrices including at least one non-zero element and the operation units storing the sub-matrices including at least one non-zero element.

Abstract: Techniques are described for assigning users to swarms based on skill and generating recommendations for increasing skill proficiency. In some implementations, a request specifying a set of requirements for completing a task includes at least one required skill, optionally in combination with a required minimum proficiency value(s). Metrics can be generated based on statistical analysis of instances in which a task is at least one of: (i) assigned to a user who is not associated with a required skill, (ii) assigned to a user whose proficiency value is below a required minimum proficiency value, or (iii) assigned after a delay due to unavailability of a user who is associated with a required skill. The computer system can identify a first skill for improving the metrics, identify a user for becoming associated with the first skill, and send a notification recommending an online learning resource relating to the first skill.

Abstract: A memory device includes: a memory array used for implementing neural networks (NN); and a controller coupled to the memory array. The controller is configured for: in updating and writing unrewritable data into the memory array in a training phase, marching the unrewritable data into a buffer zone of the memory array; and in updating and writing rewritable data into the memory array in the training phase, marching the rewritable data by skipping the buffer zone.

Abstract: A memory device includes: a memory array used for implementing neural networks (NN), the NN including a plurality of layers; and a controller coupled to the memory array, the controller being configured for: determining a computation duration of a first data of a first layer of the plurality of layers; selecting a first program operation if the computation duration of the first data of the first layer is shorter than a threshold; and selecting a second program operation if the computation duration of the first data of the first layer is longer than the threshold, wherein the second program operation has a longer program pulse time than the first program operation.

Abstract: The present invention provides a wireless communication circuitry including a processor, a communication path and a channel detection path. The communication path is configured to wirelessly communicate with an electronic device by using a first channel. The channel detection path is configured to detect at least one channel different from the first channel to generate a detection result while the communication path is wirelessly communicating with the electronic device by using the first channel. The processor determines a second channel based on the detection result, and the processor controls the communication path to switch to the second channel from the first channel to communicate with the electronic device.

Abstract: Disclosed is a memory device and an operation method thereof. The operation method of memory device, comprising: programming a plurality of sub-matrices including at least one of non-zero element of a rearranged matrix to a plurality of operation units of the memory device; and programming a mapping table into a working memory of a memory device. The rearranged matrix is generated by rearrange a plurality of columns and a plurality of rows of an original matrix according to the positions of a plurality of non-zero elements of the original matrix. The mapping table comprises a correspondence of row indexes between the original matrix and the rearranged matrix, a correspondence of column indexes between the original matrix and the rearranged matrix and a correspondence between the sub-matrices including at least one non-zero element and the operation units storing the sub-matrices including at least one non-zero element.

Abstract: A data management method for a memory is provided. The memory includes memory pages. Each of the memory pages includes memory cells. A data update command corresponding to a logical address is received. The logical address maps to a physical address of a target memory page before receiving the data update command. First and second reading voltages are applied to obtain at least a first and a second target memory cell to be sanitized in the target memory page of the memory pages, a first programming voltage is applied to change the logical state of the first target memory cell to a logical state with a higher threshold voltage, and a second programming voltage is applied to change the logical state of the second target memory cell to a logical state with a higher threshold voltage. The first programming voltage is different from the second programming voltage.

Abstract: The present disclosure provides a memory system, a method of operating memory, and a non-transitory computer readable storage medium. The memory system includes a memory chip and a controller. The controller is coupled with the memory chip, which the controller is configured to: receive a first data corresponding to a first version from a file system in order to store the first data corresponding to the first version in a first page of the flash memory chip; and program the first data corresponding to a second version in the first page in response to the first data of the second version, which the second version is newer than the first version.

Abstract: A data management method for a memory is provided. The memory includes memory pages. Each of the memory pages includes memory cells. A data update command corresponding to a logical address is received. The logical address maps to a physical address of a target memory page before receiving the data update command. First and second reading voltages are applied to obtain at least a first and a second target memory cell to be sanitized in the target memory page of the memory pages, a first programming voltage is applied to change the logical state of the first target memory cell to a logical state with a higher threshold voltage, and a second programming voltage is applied to change the logical state of the second target memory cell to a logical state with a higher threshold voltage. The first programming voltage is different from the second programming voltage.

Abstract: An in-memory computing method and apparatus, adapted for a processor to perform MAC operations on a memory, are provided. In the method, a format of binary data of weights is transformed from a floating-point format into a quantized format by truncating at least a portion of fraction bits of the binary data and calculating complements of remaining bits, and programming the transformed binary data into cells of the memory. A tuning procedure is performed by iteratively inputting binary data of input signals into the memory, integrating outputs of the memory, and adjusting the weights programmed to the cells based on the integrated outputs. The binary data of the weights is reshaped based on a probability of reducing bits with a value of one in the binary data of each weight. The tuning procedure is repeated until an end condition is met.

Abstract: The present invention provides a wireless communication circuitry including a processor, a communication path and a channel detection path. The communication path is configured to wirelessly communicate with an electronic device by using a first channel. The channel detection path is configured to detect at least one channel different from the first channel to generate a detection result while the communication path is wirelessly communicating with the electronic device by using the first channel. The processor determines a second channel based on the detection result, and the processor controls the communication path to switch to the second channel from the first channel to communicate with the electronic device.

Abstract: A memory management method includes: performing a bloom filtering operation on a plurality of logic block addresses to determine a read and written frequency of each of the logic block addresses; setting a first program/erase (P/E) cycle threshold and a second P/E cycle threshold value, wherein the first P/E cycle threshold value is smaller than the second P/E cycle threshold value; dividing each of physical memory blocks into a first type memory block, a second type memory block or a third type memory block according to the first P/E cycle threshold value and the second P/E cycle threshold value; and, allocating each of the logic block addresses to the first type memory block, the second type memory block or the third type memory block according to the read and written frequency of corresponding logic block addresses.

Abstract: An operation method of an artificial neural network is provided. The operation method includes: dividing input information into a plurality of sub-input information, and expanding kernel information to generate expanded kernel information; performing a Fast Fourier Transform (FFT) on the sub-input information and the expanded kernel information to respectively generate a plurality of frequency domain sub-input information and frequency domain expanded kernel information; respectively performing a multiplying operation on the frequency domain expanded kernel information and the frequency domain sub-input information to respectively generate a plurality of sub-feature maps; and performing an inverse FFT on the sub-feature maps to provide a plurality of converted sub-feature maps for executing a feature extraction operation of the artificial neural network.