Abstract: Disclosed are an application downloading processing method, an application downloading processing apparatus, a application downloading processing device, and a storage medium. The application downloading processing method includes obtaining a download link of application software. The download link is used for downloading an installation package of the application software. If network disconnection occurs before the downloading of the installation package is completed, caching the download link locally, and waiting for network reconnection. If removal information is obtained after the network connection is restored, canceling a downloading operation of the application software according to the removal information, and deleting the locally cached download link. The above technical solutions solve the problem of waste of an internal memory caused by downloading and installation of a removed application to the existing smart watch for kids.

Abstract: An information interaction method and apparatus, an electronic device and a storage medium are provided, the method comprising: displaying a preset first special effect element in a virtual reality space; determining whether a spatial relationship between a target control part controlled by a user and displayed in the virtual reality space and the first special effect element meets a preset condition; and in response to determining that the preset condition is met, displaying a second special effect associated with the first special effect element.

Abstract: An electronic apparatus includes: an artificial intelligence AI processor, configured to select a first image processing model from a plurality of image processing models based on scenario information. The AI processor performs first image signal processing on a first image signal by using the first image processing model, to obtain a second image signal. The first image signal is obtained based on first image data output by an image sensor. The scenario information represents feature classification of the first image signal. An image signal processor ISP, configured to perform second image signal processing on the second image signal, obtains a first image processing result. The electronic apparatus provided in embodiments of this application can improve an image processing effect.

Abstract: Embodiments of this disclosure provide an electronic apparatus and an image processing method of the electronic apparatus. The electronic apparatus includes: an artificial intelligence (AI) processor, configured to perform first image signal processing on a first image signal to obtain a second image signal, where the first image signal is obtained based on image data output by an image sensor; and an image signal processor (ISP), configured to perform second image signal processing on the second image signal to obtain an image processing result. In this way, image processing can be flexibly performed by the ISP in combination with the AI processor, and the image processing result is improved.

Abstract: Systems and processes for generating audio books from text are provided. An example process includes, at an electronic device having one or more processors and memory: receiving a text including at least a first subset and a second subset, wherein at least a portion of the first subset overlaps with at least a portion of the second subset; determining, based on the text, a prosody for a speech output, wherein the prosody is representative of a genre; determining a semantic meaning of the text; and generating, based on the prosody and the semantic meaning, the speech output of the text.

Abstract: In described examples, a boost converter includes an inductor, a voltage input, a current regulator, an intermediate node, a transistor, and a regulation circuit. The inductor has first and second terminals. The voltage input provides an input voltage, and is coupled to the first inductor terminal. The current regulator has current regulator input and output. The current regulator input is coupled to the second inductor terminal. The current regulator allows current to flow from the current regulator input to the current regulator output, and not vice versa. The intermediate node provides a node voltage. The transistor includes a source, a drain, and a gate. The drain is coupled to the current regulator output via the intermediate node. The regulation circuit includes a first regulation input coupled to receive the input voltage, a second regulation input coupled to the intermediate node, and a regulation output coupled to the gate.

Abstract: A voltage converter includes an inductor, a transistor, a comparator, an error amplifier, and a slope generator circuit. The transistor has a control input and first and second transistor current terminals. The first current terminal is coupled to the inductor. The comparator has first and second comparator inputs and a comparator output. The comparator output is usable to control the transistor's control input. The error amplifier has an error amplifier input and an error amplifier output. The error amplifier output is coupled to the first comparator input. The slope generator circuit is coupled to at least one of the first or second comparator inputs. The slope generator circuit is configured to generate a slope compensation current which, during at least a portion of each cycle of operation of the voltage regulator, varies approximately exponentially with respect to time.

Abstract: A DC-DC converter control circuit includes an error amplifier, a voltage-to-current conversion circuit, an oscillator circuit, and a pulse frequency modulation (PFM) control circuit. The error amplifier is configured to generate a difference voltage as a difference of an output voltage of the DC-DC converter circuit and a reference voltage. The voltage-to-current conversion circuit configured to convert the difference voltage to a difference current. The oscillator circuit is configured to generate a clock signal at a predetermined frequency for pulse width modulation. The PFM control circuit is configured to disable the oscillator circuit, based on the difference current, for PFM operation.

Abstract: A voltage converter includes an inductor, a transistor, a comparator, an error amplifier, and a slope generator circuit. The transistor has a control input and first and second transistor current terminals. The first current terminal is coupled to the inductor. The comparator has first and second comparator inputs and a comparator output. The comparator output is usable to control the transistor's control input. The error amplifier has an error amplifier input and an error amplifier output. The error amplifier output is coupled to the first comparator input. The slope generator circuit is coupled to at least one of the first or second comparator inputs. The slope generator circuit is configured to generate a slope compensation current which, during at least a portion of each cycle of operation of the voltage regulator, varies approximately exponentially with respect to time.

Abstract: A converter system includes a first switch, a first sensing unit configured to generate a first sensed signal proportional to a current through the first switch, a second sensing unit (118) configured to generate a second sensed signal based on a difference between a reference voltage and a feedback voltage, a DC compensation unit configured to generate a slope peak DC signal relative to a slope peak of a slope compensation signal, and a signal combination unit configured to generate a control signal based on the first and second sensed signals, the slope compensation signal and the slope peak DC signal to switch off the first switch.

Abstract: A DC-DC converter control circuit includes an error amplifier, a voltage-to-current conversion circuit, an oscillator circuit, and a pulse frequency modulation (PFM) control circuit. The error amplifier is configured to generate a difference voltage as a difference of an output voltage of the DC-DC converter circuit and a reference voltage. The voltage-to-current conversion circuit configured to convert the difference voltage to a difference current. The oscillator circuit is configured to generate a clock signal at a predetermined frequency for pulse width modulation. The PFM control circuit is configured to disable the oscillator circuit, based on the difference current, for PFM operation.

Abstract: A converter system includes a first switch, a first sensing unit configured to generate a first sensed signal proportional to a current through the first switch, a second sensing unit (118) configured to generate a second sensed signal based on a difference between a reference voltage and a feedback voltage, a DC compensation unit configured to generate a slope peak DC signal relative to a slope peak of a slope compensation signal, and a signal combination unit configured to generate a control signal based on the first and second sensed signals, the slope compensation signal and the slope peak DC signal to switch off the first switch.

Abstract: A DC-DC converter controller includes a transistor driver, a flip-flop, a comparator, an integrator circuit, a switch, and a pulse generator circuit. The flip-flop includes an output coupled to an input of the transistor driver. The comparator includes an output coupled an input of the flip-flop. The integrator circuit includes an output coupled to an input of the comparator. The switch includes a first terminal coupled to the output of the integrator circuit, and a second terminal coupled to ground. The pulse generator circuit includes an input coupled to an output of the transistor driver, and an output coupled to a third terminal of the switch.

Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.

Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.

Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.

Abstract: A differential receiver with reduced common mode induced propagation delay variance. One implementation of a differential receiver includes a first differential amplifier, a second differential amplifier, and a first current source. The first differential amplifier includes a first transistor pair. The second differential amplifier includes a second transistor pair. The first current source is coupled to a drain node of a first transistor of the first transistor pair. The first current source is configured to generate a variable first current at the drain node as of function of a sum of a variable tail current of the first differential amplifier and a variable tail current of the second differential amplifier.

Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.

Abstract: Some embodiments of the present invention provide a method and apparatus for a Vernier ring time to digital converter having a single clock input and an all digital circuit that calculates a fixed delay relationship between a set of slow buffers and fast buffers. A method for calibrating a Vernier Delay Line of a TDC, comprising the steps of inputting a reference clock to a slow buffer and to a fast buffer, determining a delay ratio of the slow buffer and fast buffer; and adjusting the delay ratio of the slow buffer and fast buffer to a fixed delay ratio value wherein an up-down accumulator generates control signals to adjust the slow buffer.

Abstract: A differential receiver with reduced common mode induced propagation delay variance. One implementation of a differential receiver includes a first differential amplifier, a second differential amplifier, and a first current source. The first differential amplifier includes a first transistor pair. The second differential amplifier includes a second transistor pair. The first current source is coupled to a drain node of a first transistor of the first transistor pair. The first current source is configured to generate a variable first current at the drain node as of function of a sum of a variable tail current of the first differential amplifier and a variable tail current of the second differential amplifier.