Abstract: An adaptive digital phase locked loop comprises: a digital configurable phase detector for receiving a reference signal and a feedback signal and for generating a detection signal indicative of a phase/frequency difference between the reference signal and the feedback signal; a configurable digital loop filter for filtering the DPFD detection signal; a digital locking monitor for monitoring polarity transitions of the detection signal and adaptively switching the locking modes and DCO tuning resolution; and a DCO for generating the feedback signal as a function of the detection signal.

Abstract: An adaptive digital phase locked loop comprises: a digital configurable phase detector for receiving a reference signal and a feedback signal and for generating a detection signal indicative of a phase/frequency difference between the reference signal and the feedback signal; a configurable digital loop filter for filtering the DPFD detection signal; a digital locking monitor for monitoring polarity transitions of the detection signal and adaptively switching the locking modes and DCO tuning resolution; and a DCO for generating the feedback signal as a function of the detection signal.

Abstract: A method for digital phase detection, comprises the steps of: providing a reference clock; receiving a feedback clock; determining a timing difference between the reference clock and the feedback clock; determining a polarity that indicates the leading or lagging relationship between the reference clock and the feedback clock; adaptively selecting one of at least two operating modes for generating a quantized level indicative of the timing difference, wherein in a first operating mode the quantized level is a constant maximum value and wherein in a second operating mode the quantized level is proportional to the timing difference; and generating a digital phase detection output as a combination of the polarity and the quantized level.

Abstract: A bias current generating circuit generates a reliable and consistent bias current, irrespective of variation in applied power, process and temperature. In one embodiment, the bias current generator generates a bias current using a PTAT current generator and an IPTAT current generator comprising exclusively active circuit elements, for example transistors. No passive elements, such as resistors, are employed. The generated bias current is substantially a function of the respective aspect ratios of transistors of current paths of the device. In this manner, the resulting generated bias current has greatly reduced susceptibility to variation in applied power, process and temperature.

Abstract: A bias current generating circuit generates a reliable and consistent bias current, irrespective of variation in applied power, process and temperature. In one embodiment, the bias current generator generates a bias current using a PTAT current generator and an IPTAT current generator comprising exclusively active circuit elements, for example transistors. No passive elements, such as resistors, are employed. The generated bias current is substantially a function of the respective aspect ratios of transistors of current paths of the device. In this manner, the resulting generated bias current has greatly reduced susceptibility to variation in applied power, process and temperature.