Abstract: A power module of a square flat pin-free packaging structure for suppressing the power module from being excessively high in local temperature. The power module includes an insulating resin, a driving chip, a plurality of power chips, and a plurality of metal electrode contacts. The driving chip, the power chips, and the metal electrode contacts are electrically connected through a metal lead according to a predetermined circuit. A plurality of metal heat dissipating disks used for heat dissipation of the power chips and a driving chip lead frame are disposed at the bottom of the insulating resin. A plurality of metal power chip lead frames are disposed on the metal heat dissipating disks, the power chips are disposed on the power chip lead frames, and the drain electrodes of the power chips are electrically connected to the metal heat dissipating disks.

Abstract: A control method for improving dynamic response of switch power is based on a closed-loop control system comprising a sampling module, a dynamic control module, an error calculation module, a PID module, a mode control module, and a PWM module. The sampling module samples an output voltage Vo, and the dynamic control module compares the output voltage Vo with a set maximum voltage Vomax, a set minimum voltage Vomin, and a reference voltage Vref, so as to determine whether to adopt a dynamic mode. In the dynamic mode, when the output voltage Vo changes greatly, the output voltage Vo is rapidly restored to a stable voltage by inputting large power or small power.

Abstract: A power module of a square flat pin-free packaging structure for suppressing the power module from being excessively high in local temperature. The power module includes an insulating resin, a driving chip, a plurality of power chips, and a plurality of metal electrode contacts. The driving chip, the power chips, and the metal electrode contacts are electrically connected through a metal lead according to a predetermined circuit. A plurality of metal heat dissipating disks used for heat dissipation of the power chips and a driving chip lead frame are disposed at the bottom of the insulating resin. A plurality of metal power chip lead frames are disposed on the metal heat dissipating disks, the power chips are disposed on the power chip lead frames, and the drain electrodes of the power chips are electrically connected to the metal heat dissipating disks.

Abstract: A transverse ultra-thin insulated gate bipolar transistor having current density includes: a P substrate, where the P substrate is provided with a buried oxide layer thereon, the buried oxide layer is provided with an N epitaxial layer thereon, the N epitaxial layer is provided with an N well region and P base region therein, the P base region is provided with a first P contact region and an N source region therein, the N well region is provided with an N buffer region therein, the N well region is provided with a field oxide layer thereon, the N buffer region is provided with a P drain region therein, the N epitaxial layer is provided therein with a P base region array including a P annular base region, the P base region array is located between the N well region and the P base region, the P annular base region is provided with a second P contact region and an N annular source region therein, and the second P contact region is located in the N annular source region.

Abstract: A high-current, N-type silicon-on-insulator lateral insulated-gate bipolar transistor, including: a P-type substrate, a buried-oxide layer disposed on the P-type substrate, an N-type epitaxial layer disposed on the oxide layer, and an N-type buffer trap region. A P-type body region and an N-type central buffer trap region are disposed inside the N-type epitaxial layer; a P-type drain region is disposed in the buffer trap region; N-type source regions and a P-type body contact region are disposed in the P-type body region; an N-type base region and a P-type emitter region are disposed in the buffer trap region; gate and field oxide layers are disposed on the N-type epitaxial layer; polycrystalline silicon gates are disposed on the gate oxide layers; and a passivation layer and metal layers are disposed on the surface of the symmetrical transistor. P-type emitter region output and current density are improved without increasing the area of the transistor.

Abstract: A transverse ultra-thin insulated gate bipolar transistor having current density includes: a P substrate, where the P substrate is provided with a buried oxide layer thereon, the buried oxide layer is provided with an N epitaxial layer thereon, the N epitaxial layer is provided with an N well region and P base region therein, the P base region is provided with a first P contact region and an N source region therein, the N well region is provided with an N buffer region therein, the N well region is provided with a field oxide layer thereon, the N buffer region is provided with a P drain region therein, the N epitaxial layer is provided therein with a P base region array including a P annular base region, the P base region array is located between the N well region and the P base region, the P annular base region is provided with a second P contact region and an N annular source region therein, and the second P contact region is located in the N annular source region.

Abstract: An isolation structure of a high-voltage driving circuit includes a P-type substrate and a P-type epitaxial layer; a high voltage area, a low voltage area and a high and low voltage junction terminal area are arranged on the P-type epitaxial layer; a first P-type junction isolation area is arranged between the high and low voltage junction terminal area and the low voltage area, and a high-voltage insulated gate field effect tube is arranged between the high voltage area and the low voltage area; two sides of the high-voltage insulated gate field effect tube and an isolation structure between the high-voltage insulated gate field effect tube and a high side area are formed as a second P-type junction isolation area.

Abstract: A high-current, N-type silicon-on-insulator lateral insulated-gate bipolar transistor, including: a P-type substrate, a buried-oxide layer disposed on the P-type substrate, an N-type epitaxial layer disposed on the oxide layer, and an N-type buffer trap region. A P-type body region and an N-type central buffer trap region are disposed inside the N-type epitaxial layer; a P-type drain region is disposed in the buffer trap region; N-type source regions and a P-type body contact region are disposed in the P-type body region; an N-type base region and a P-type emitter region are disposed in the buffer trap region; gate and field oxide layers are disposed on the N-type epitaxial layer; polycrystalline silicon gates are disposed on the gate oxide layers; and a passivation layer and metal layers are disposed on the surface of the symmetrical transistor. P-type emitter region output and current density are improved without increasing the area of the transistor.

Abstract: An isolation structure of a high-voltage driving circuit includes a P-type substrate and a P-type epitaxial layer; a high voltage area, a low voltage area and a high and low voltage junction terminal area are arranged on the P-type epitaxial layer; a first P-type junction isolation area is arranged between the high and low voltage junction terminal area and the low voltage area, and a high-voltage insulated gate field effect tube is arranged between the high voltage area and the low voltage area; two sides of the high-voltage insulated gate field effect tube and an isolation structure between the high-voltage insulated gate field effect tube and a high side area are formed as a second P-type junction isolation area.

Abstract: A silicon on insulator N type semiconductor device, includes a N type drift region, a P type deep well, an N type buffer well, a P type drain region, an N type source region and a P type body contact region; a field oxide layer and a gate oxide layer arranged on a silicon surface, and a polysilicon lattice arranged on the gate oxide layer; and an N type triode drift region, a P type deep well, an N type triode buffer well, a P type emitting region, an N type base region, an N type source region and a P type body contact region; a field oxide layer and a gate oxide layer arranged on a silicon surface, and a polysilicon lattice arranged on the gate oxide layer.

Abstract: A switching power supply with a quick transient response is provided. A hysteretic control loop which comprises a hysteretic controller (117) and a control signal gate (116) is added to the original PWM control loop of the switching power supply. The hysteretic controller (117) is used to detect an output voltage (Vout) of the switching power supply and compare the output voltage (Vout) of the switching power supply with a reference voltage (Vref). When a load current (Iout) of the switching power supply is suddenly changed, the output voltage (Vout) of the switching power supply fluctuates. If the output voltage (Vout) of the switching power supply is in a setting range of the hysteretic voltage, output terminals (SELp, SELn) of the hysteretic controller (117) are in a low potential, and the control signal gate (116) selects output signals (Qp1, Qn1) from a PWM controller (101) as input signals of a gate signal drive circuit (106).

Abstract: A switch level circuit (110) with dead time self-adapting control, which minimizes the switching loss in a switching power supply converter with synchronous rectification by changing a dead time between a high-side control transistor (10) and a low-side synchronous rectifying transistor (11). The switch level circuit (110) includes the high-side control transistor (10) and the low-side synchronous rectifying transistor (11) which are controlled to be on and off by external control signals, and a waveform with a given duty cycle is outputted at a node (LX) between the two transistors. The switch level circuit (110) also includes a control module for adjusting the dead time.

Abstract: A silicon on insulator integrated high-current N type combined semiconductor device, which can improve the current density, comprises a P type substrate and a buried oxide layer arranged thereon. A P type epitaxial layer divided into a region I and a region II is arranged on the buried oxide layer. The region I comprises an N type drift region, a P type deep well, an N type buffer well, a P type drain region, an N type source region and a P type body contact region; a field oxide layer and agate oxide layer are arranged on a silicon surface, and a polysilicon lattice is arranged on the gate oxide layer. The region II comprises an N type triode drift region, a P type deep well, an N type triode buffer well, a P type emitting region, an N type base region, an N type source region and a P type body contact region; a field oxide layer and a gate oxide layer are arranged on a silicon surface, and a polysilicon lattice is arranged on the gate oxide layer.

Abstract: A switching power supply with a quick transient response is provided. A hysteretic control loop which comprises a hysteretic controller (117) and a control signal gate (116) is added to the original PWM control loop of the switching power supply. The hysteretic controller (117) is used to detect an output voltage (Vout) of the switching power supply and compare the output voltage (Vout) of the switching power supply with a reference voltage (Vref). When a load current (Iout) of the switching power supply is suddenly changed, the output voltage (Vout) of the switching power supply fluctuates. If the output voltage (Vout) of the switching power supply is in a setting range of the hysteretic voltage, output terminals (SELp, SELn) of the hysteretic controller (117) are in a low potential, and the control signal gate (116) selects output signals (Qp1, Qn1) from a PWM controller (101) as input signals of a gate signal drive circuit (106).

Abstract: A switch level circuit (110) with dead time self-adapting control, which minimizes the switching loss in a switching power supply converter with synchronous rectification by changing a dead time between a high-side control transistor (10) and a low-side synchronous rectifying transistor (11). The switch level circuit (110) includes the high-side control transistor (10) and the low-side synchronous rectifying transistor (11) which are controlled to be on and off by external control signals, and a waveform with a given duty cycle is outputted at a node (LX) between the two transistors. The switch level circuit (110) also includes a control module for adjusting the dead time.

Abstract: A computer readable medium configured to approximate the integral of the product of a plurality of functions includes logic configured to factor the plurality of functions into a set of fixed functions and one varying function, logic configured to determine a first vector that represents the product of the fixed functions in the wavelet domain, logic configured to determine a second vector that represents the one varying function in the wavelet domain, and logic configured to determine an inner product of the first vector and the second vector.

Abstract: A computer readable medium is configured to determine the integral of the product of a plurality of functions. The computer readable medium includes logic configured to project each function of the plurality of functions into the wavelet domain, logic configured to encode basis coefficients of each function in a wavelet tree, each function being encoded in at least one wavelet tree such that the plurality of functions are represented in the wavelet domain by a plurality of wavelet trees, and logic configured to traverse direct paths through the plurality of wavelet trees to determine the integral of the product of the functions represented by the wavelet trees, along which direct paths an integral coefficient may be nonzero.

Abstract: A method of rendering a graphical scene includes determining a plurality of functions that contribute to a light transport model of the scene, projecting each function of the plurality of functions into the wavelet domain, encoding basis coefficients of each function in a wavelet tree, each function being encoded in at least one wavelet tree such that the plurality of functions are represented in the wavelet domain by a plurality of wavelet trees, traversing direct paths through the plurality of wavelet trees, along which direct paths an integral coefficient may be nonzero, to determine the radiance of a point in the scene, and rendering the scene.

Abstract: A method of rendering a graphical scene includes determining a plurality of functions that contribute to a light transport model of a scene, factoring the plurality of functions into a set of fixed functions and one varying function, determining a first radiance transfer vector that represents the product of the fixed functions in the wavelet domain, determining a second radiance transfer vector that represents the one varying function in the wavelet domain, determining an inner product of the first and second radiance transfer vectors to approximate a radiance of a point x in the scene, and rendering the scene.

Abstract: The low power consumption CMOS high voltage driving circuit relates to a kind of high voltage driving circuit for output driving, and there is an out buffer stage between the output end of the level switch stage and the input end of the high voltage output stage, comprising a high voltage PMOS pipe and a high voltage NMOS pipe. The source of the high voltage PMOS pipe is connected with the power supply, its gate electrode is connected with the output end of the upper level out buffer unit as the input end of the current level out buffer unit. The source of the high voltage NMOS pipe is put to earth, and its gate electrode serves as the receiving end of the 3ith sequence signal. The drain region of the high voltage PMOS pipe is connected with that of the high voltage NMOS pipe and is connected with the input end of the lower level out buffer unit as the output end of the current level out buffer unit.