Abstract: A lossless exciting current sampling circuit for an isolated converter includes first and second voltage sampling circuits and a subtraction circuit formed by an operational amplifier. The two sampling circuits sample voltages of the primary winding of an isolation transformer, with outputs fed into the subtracter. The subtracter output is the circuit's output. RC low-pass filters with large time constants are used as primary voltage sampling circuits, realizing integration of voltage differences between the exciting inductance terminals, enabling lossless current sampling without resistors or transformers. The current sampling result is utilized for volt-second balance control, realized along with a hold circuit and comparator which compares the sampling hold result with the current sampling result to generate a control signal.

Abstract: The present disclosure provides a DMOS device with a junction field plate and its manufacturing method. A drain region is located on a surface of a semiconductor substrate. A source region is located in the semiconductor substrate at a bottom of a first trench. A gate electrode is located at the bottom of the first trench. The junction field plate improves an effect on reducing surface resistance. At the same time, a depth of trenches in the DMOS device may be reduced, and thereby a depth-to-width ratio of the device is reduced, improving the feasibility of increasing a voltage resistance level. Both the source region and the drain region in the DMOS device are led out on a same surface. A second doped polycrystalline silicon layer includes a first doped sublayer and a second doped sublayer with different conduction types.

Abstract: An isolation structure for an N epitaxy-based silicon carbide device, and an N epitaxy-based silicon carbide high and low voltage integrated device and a preparation method therefor are provided. The isolation structure includes N-type substrate, a first isolation trench and a second isolation trench to form a high-voltage region, a low-voltage region and a level shift region, a second P-type doped region is arranged at the bottom of the low-voltage region and of the level shift region, a second N-type doped region is arranged on the second P-type doped region in the low-voltage region, and back-to-back PN junctions are formed by the N-type drift region, the second P-type doped region in the low-voltage region, and the second N-type doped region. A DMOS device is arranged in a high-voltage region, low-voltage devices are arranged in a low-voltage region, and an LDMOS device is arranged in a level shift region.

Abstract: In one aspect, a laterally diffused metal oxide semiconductor (LDMOS) device includes at least one cell structure. The cell structure includes: a substrate; a N-type first well region disposed in the substrate; the first well region being provided with a first region, an isolation region, and a second region that are sequentially arranged in a first direction; a P-type first doped region and a P-type second doped region, the first doped region being located in the first region, and the second doped region being located in the second region; and a P-type source region and a P-type drain region disposed in the substrate and located on two sides of the first doped region in a second direction. The first direction is a width direction of a conductive channel. The second direction is a length direction of the conductive channel.

Abstract: An IGZO thin-film transistor and a method for manufacturing same. The method includes: acquiring a substrate; forming an IGZO layer on the substrate by a solution process; doping V impurities on a surface of the IGZO layer by a spin doping process; forming a source electrode at one side of the IGZO layer, and forming a drain electrode at the other side; forming a gate dielectric layer on the doped IGZO layer; and forming a gate electrode on the gate dielectric layer.

Abstract: In one aspect, a silicon-on-insulator semiconductor device includes: a substrate; a buried dielectric layer disposed on the substrate; a first electrode; a second electrode; and a drift region disposed on the buried dielectric layer. An upper surface of the drift region forms a drop structure including a first side adjacent to the first electrode, a second side adjacent to the second electrode, and a transition region between the first side and the second side. An upper surface of the second side is higher than a bottom surface of the first side, such that a thickness of the drift region at the second side is greater than that at the first side. The first electrode and the second electrode are configured such that a voltage applied to the second electrode is greater than a voltage applied to the first electrode when a reverse bias voltage is applied to the device.

Abstract: A high-voltage resistant enhancement-mode GaN device with enhanced integration is provided. A nucleating layer, a buffer layer, and a GaN layer are sequentially stacked on a silicon substrate. A p-GaN region and an AlGaN barrier layer are formed on the GaN layer, with a first n-GaN region embedded in the p-GaN region. A first metal electrode is connected to the first n-GaN region, while a second metal electrode, serving as a gate, is placed on a first SiO2 oxide layer above the p-GaN region. A fourth metal electrode acts as a drain on the AlGaN barrier layer. A second n-GaN region divides the AlGaN barrier into two sections, with a third metal electrode on a second SiO2 oxide layer connected to the first metal electrode as a source. The second n-GaN region and the third metal electrode mitigate edge effects.

Abstract: A gallium nitride power device with wide-range working gate voltage structurally includes a base and isolation regions, wherein the base is provided with a substrate, a nucleating layer, a buffer layer, a channel layer, a barrier layer and a passivation layer in sequence from the bottom up, and a voltage-limiting tube region, a power tube region and a bleed-off tube region are arranged on the barrier layer.

Abstract: An inductor current estimation method for a DC-DC switching power supply using a voltage sampling module, a data conversion module, a switching signal counting module, an inductor voltage calculation module and a digital filter module, comprising: processing an input voltage and an output voltage by the voltage sampling module and the data conversion module to obtain a converted input voltage and a converted output voltage which have a same number of bits; comparing a node voltage with a reference voltage, and then obtaining a duty cycle by the switching signal counting module; and then, outputting an average voltage of two terminals of an inductor and a parasitic resistor by the inductor voltage calculation module, and finally, obtaining an estimated inductor current by the digital filter module.

Abstract: A conductive channel structure for SiC devices, a fully integrated SiC device and a fully integrated manufacturing process thereof are provided. The fully integrated SiC device features a low-voltage region, a first high-voltage region and a second high-voltage region separated by isolation structures on the same SiC-based chip, and integrates first and second conductivity type MOS devices. The first and second conductivity type devices employ first and second conductivity type conductive channels respectively with alternating N-type and P-type first or second conductivity type areas above them. The manufacturing process includes sequentially stacking a second conductivity type epitaxial layer and buffer layer on an N-type substrate; and within the second conductivity type buffer layer, arranging first conductivity type well regions, heavily doped regions, channel regions, second conductivity type well regions, isolation structures, heavily doped regions, and channel regions.

Abstract: A conductive channel structure for SiC devices, a fully integrated SiC device and a fully integrated manufacturing process thereof are provided. The fully integrated SiC device features a low-voltage region, a first high-voltage region and a second high-voltage region separated by isolation structures on the same SiC-based chip, and integrates first and second conductivity type MOS devices. The first and second conductivity type devices employ first and second conductivity type conductive channels respectively with alternating N-type and P-type first or second conductivity type areas above them. The manufacturing process includes sequentially stacking a second conductivity type epitaxial layer and buffer layer on an N-type substrate; and within the second conductivity type buffer layer, arranging first conductivity type well regions, heavily doped regions, channel regions, second conductivity type well regions, isolation structures, heavily doped regions, and channel regions.

Abstract: A non-isolated resonant gate drive circuit includes a PMOS drive network, an NMOS clamping circuit and an inductor. The PMOS drive network and the NMOS clamping circuit are connected in parallel to two terminals of the inductor. Input signals of the PMOS drive network are provided by a function generator connected to a drive chip, drive signals are output via an output port vgsr1 and an output port vgsr2 after the input signals are processed by the PMOS drive network, the NMOS clamping circuit and the inductor, the NMOS clamping circuit is used for controlling the state of the output port vgsr1 and the output port vgsr2 to change, and the inductor forms LC resonance together with a gate capacitor Cgsr1 and a gate capacitor Cgsr2 in the NMOS clamping circuit to recover energy in a process of turning off the drive circuit.

Abstract: A horizontal Hall device includes a substrate layer and a BOX layer arranged on the substrate layer, where an epitaxial layer is arranged on the BOX layer, a well layer is arranged on the epitaxial layer, an STI layer is arranged on the well layer, a pair of induction electrodes and a pair of bias electrodes are arranged on the STI layer, ground electrodes are arranged on the epitaxial layer, and current barrier layers are arranged between the induction electrodes and the adjacent bias electrodes.

Abstract: A non-isolated resonant gate drive circuit includes a PMOS drive network, an NMOS clamping circuit and an inductor. The PMOS drive network and the NMOS clamping circuit are connected in parallel to two terminals of the inductor. Input signals of the PMOS drive network are provided by a function generator connected to a drive chip, drive signals are output via an output port vgsr1 and an output port vgsr2 after the input signals are processed by the PMOS drive network, the NMOS clamping circuit and the inductor, the NMOS clamping circuit is used for controlling the state of the output port vgsr1 and the output port vgsr2 to change, and the inductor forms LC resonance together with a gate capacitor Cgsr1 and a gate capacitor Cgsr2 in the NMOS clamping circuit to recover energy in a process of turning off the drive circuit.

Abstract: An in-situ detection robot and method for geological information without disturbance of in-situ stress, including a sleeve, a drilling unit set at the top of the sleeve, a dumping unit set inside the sleeve, and a support propulsion unit is set outside the sleeve, the top of the dumping unit extends into the drilling unit, a detection unit is set between the drilling unit and the support propulsion unit, and the robot tail is connected to a control unit; the dumping unit is used to discharge soil drilled from a hole of the drilling unit to the ground, the support propulsion unit is used to realize support, the detection unit is used to detect geological information of surrounding environment of the robot, the control unit is used to control the drilling unit, the support propulsion unit and the detection unit, and the control unit collects and processes the geological information.

Abstract: A horizontal Hall device includes a substrate layer and a BOX layer arranged on the substrate layer, where an epitaxial layer is arranged on the BOX layer, a well layer is arranged on the epitaxial layer, an STI layer is arranged on the well layer, a pair of induction electrodes and a pair of bias electrodes are arranged on the STI layer, ground electrodes are arranged on the epitaxial layer, and current barrier layers are arranged between the induction electrodes and the adjacent bias electrodes.

Abstract: A lossless exciting current sampling circuit for an isolated converter includes first and second voltage sampling circuits and a subtraction circuit formed by an operational amplifier. The two sampling circuits sample voltages of the primary winding of an isolation transformer, with outputs fed into the subtracter. The subtracter output is the circuit's output. RC low-pass filters with large time constants are used as primary voltage sampling circuits, realizing integration of voltage differences between the exciting inductance terminals, enabling lossless current sampling without resistors or transformers. The current sampling result is utilized for volt-second balance control, realized along with a hold circuit and comparator which compares the sampling hold result with the current sampling result to generate a control signal.

Abstract: A manufacturing method for a P-type laterally diffused metal oxide semiconductor device includes: forming a N-type buried layer in a substrate, forming a P-type region located on the N-type buried layer, and forming a mask layer located on the P-type region; patterning the mask layer to form at least two injection windows; performing N-type ion implantation by the at least two injection windows; forming an oxide layer; removing the mask layer; performing P-type ion implantation on the P-type region to form a P-type doped region; diffusing the P-type doped region to form a drift region and two P-type well regions, diffusing the high-voltage N-well doped region to form a high-voltage N-type well region, and diffusing the low-voltage N-well doped region to form a low-voltage N-type well region; and forming a source doped region, a drain doped region, and a gate.

Abstract: A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer is arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.

Abstract: The present application discloses a preparation method of SM non-woven fabrics for roof anti-slip, which belongs to the technical field of roofing materials, comprising preparing spunbond non-woven fabric raw materials, preparing spunbond non-woven fabrics, preparing meltblown non-woven fabric raw materials, preparing primary SM non-woven fabrics, and post-processing; the spunbond non-woven fabric raw materials are prepared by uniformly mixing polypropylene with a low melt flow index, polypropylene with a high melt flow index, sodium alginate, antioxidant 1010, zinc stearate, ultraviolet absorber UV-531, polyvinyl alcohol, reinforcing agent, adhesive agent, and nano titanium dioxide. The present application can avoid the problem that the SM non-woven fabrics cannot be fully bonded together and are easy to delaminate when being combined, can also solve the problem of fabric breakage during high-speed production, and can also improve the wear resistance, strength, and stiffness of SM non-woven fabrics.