Patents by Inventor Weifeng Sun

Weifeng Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105083
    Abstract: A high-speed remote landslide simulation test device with a variable angle includes a support adjustment component, slide plates, and loose leaves. The device first transmits the operation paths of adjusting the slide plate at different angles to the controller, and the personnel operates the control panel to control the support jack, the motor, and the electromagnet to start and stop through the controller, the output shaft of the motor drives the stainless steel threaded rod to rotate, the controller first energizes one electromagnet and disconnects the other three electromagnets, which can only make the stainless steel threaded rod rotate in a fixed position inside the inner threaded pipe, and the three inner threaded pipes follow the rotation direction of the stainless steel threaded rod, thus, the position of the support jack can be moved separately.
    Type: Application
    Filed: December 8, 2023
    Publication date: March 28, 2024
    Applicant: Chang'an University
    Inventors: Hengxing LAN, Mervyn LAN, Zhao CHEN, Shijie LIU, Weifeng SUN, Ning ZHANG, Bei ZHANG
  • Patent number: 11917904
    Abstract: The present application provides a perovskite solar cell, including conductive glass, a hole transport layer, a perovskite layer, an electron transport layer and a back electrode, where a passivation layer may be disposed between the hole transport layer and the perovskite layer, and the passivation layer may include an amide and/or a cation thereof, where the amide may include a compound of formula (1) and/or formula (2): where R1 and R2 are each independently selected from hydrogen, —R, —NR2, —NHR, —NH2, —OH, —OR, —NHCOR, —OCOR, and —CH2COOH, where R represents a straight or branched chain alkyl group having 1-10 carbon atoms, m is an integer of 0 to 10; and n is an integer of 1 to 10; and where Ar is selected from a C5-C10 aryl or heteroaryl group.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: February 27, 2024
    Assignee: CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED
    Inventors: Weifeng Liang, Wenming Guo, Juanjuan Sun, Bo Luan, Yongsheng Guo, Guodong Chen
  • Patent number: 11894458
    Abstract: A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: February 6, 2024
    Assignees: SOUTHEAST UNIVERSITY, CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Jiaxing Wei, Qichao Wang, Kui Xiao, Dejin Wang, Li Lu, Ling Yang, Ran Ye, Siyang Liu, Weifeng Sun, Longxing Shi
  • Patent number: 11777416
    Abstract: A flyback converter and an output voltage acquisition method therefor and apparatus thereof, wherein the output voltage acquisition method comprises the following steps: acquiring the reference output voltage of a flyback converter; sampling the current output voltage of the flyback converter within a reset time of each switching period among M continuous switching periods of the flyback converter, wherein M is a positive integer; and according to the reference output voltage and the current output voltage, sampling a dichotomy to successively approximate the current output voltage until the M switching periods are finished, and acquiring the output voltage of the flyback converter.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: October 3, 2023
    Assignees: SOUTHEAST UNIVERSITY, CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Weifeng Sun, Huaxin Zhang, Hu Zhang, Menglin Yu, Siyu Zhao, Shen Xu, Longxing Shi
  • Patent number: 11770076
    Abstract: Disclosed are a system and method for controlling an active clamp flyback (ACF) converter. The system includes: a drive module configured to control turning-on or turning-off of a main switching transistor SL and a clamp switching transistor SH; a main switching transistor voltage sampling circuit configured to sample a voltage drop between an input terminal and an output terminal of the main switching transistor SL; a first comparator connected to the main switching transistor voltage sampling circuit and configured to determine whether a sampled first sampling voltage is a positive voltage or a negative voltage; and a dead time calculation module configured to adjust, according to an output of the first comparator and a main switching transistor control signal DUTYL of a current cycle, a clamp switching transistor control signal DUTYH of next cycle outputted by the drive module.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: September 26, 2023
    Assignees: SOUTHEAST UNIVERSITY, CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Shen Xu, Minggang Chen, Wanqing Yang, Dejin Wang, Rui Jiang, Weifeng Sun, Longxing Shi
  • Patent number: 11742423
    Abstract: A laterally double-diffused metal oxide semiconductor device is provided, including: a drift region (3) having a first conductivity type; a first body region (10) disposed on the drift region (3) and having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; a first conductivity type region (13) disposed in the first body region (10); a second body region (12) disposed in the first conductivity type region (13) and having the second conductivity type; a source region (11) disposed in the second body region (12) and having the first conductivity type; and a contact region (9) disposed in the first body region (10) and having the second conductivity type.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: August 29, 2023
    Assignees: SOUTHEAST UNIVERSITY, CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Jing Zhu, Guichuang Zhu, Nailong He, Sen Zhang, Shaohong Li, Weifeng Sun, Longxing Shi
  • Publication number: 20230019004
    Abstract: A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 19, 2023
    Inventors: Jiaxing WEI, Qichao WANG, Kui XIAO, Dejin WANG, Li LU, Ling YANG, Ran YE, Siyang LIU, Weifeng SUN, Longxing SHI
  • Patent number: 11557959
    Abstract: An automatic dead zone time optimization system in a primary-side regulation flyback power supply continuous conduction mode (CCM), including a closed loop formed by a control system, including a single output digital to analog converter (DAC) midpoint sampling module, a digital control module, a current detection module, a dead zone time calculation module and a pulse-width modulation (PWM) driving module, and a controlled synchronous rectification primary-side regulation flyback converter. A primary-side current is sampled using a DAC Sampling mechanism to calculate a secondary-side average current, so as to obtain a primary-side average current and a secondary-side average current, in the case of CCM. A secondary-side current is input into the dead zone time calculation module to obtain a reasonable dead zone time; and the PWM driving module is jointly controlled by a primary-side regulation loop and the obtained dead zone time.
    Type: Grant
    Filed: December 29, 2018
    Date of Patent: January 17, 2023
    Assignees: CSMC TECHNOLOGIES FAB2 CO., LTD., SOUTHEAST UNIVERSITY
    Inventors: Shen Xu, Minggang Chen, Hao Wang, Jinyu Xiao, Wei Su, Weifeng Sun, Longxing Shi
  • Patent number: 11515395
    Abstract: A gallium nitride power device, including: a gallium nitride substrate; cathodes; a plurality of gallium nitride protruding structures arranged on the gallium nitride substrate and between the cathodes, a groove is formed between adjacent gallium nitride protruding structures; an electron transport layer, covering a top portion and side surfaces of each of the gallium nitride protruding structures; a gallium nitride layer, arranged on the electron transport layer and filling each of the grooves; a plurality of second conductivity type regions, where each of the second conductivity type regions extends downward from a top portion of the gallium nitride layer into one of the grooves, and the top portion of each of the gallium nitride protruding structures is higher than a bottom portion of each of the second conductivity type regions; and an anode, arranged on the gallium nitride layer and the second conductivity type regions.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: November 29, 2022
    Assignees: SOUTHEAST UNIVERSITY, CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Siyang Liu, Ningbo Li, Dejin Wang, Kui Xiao, Chi Zhang, Sheng Li, Xinyi Tao, Weifeng Sun, Longxing Shi
  • Publication number: 20220376094
    Abstract: An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region; the anode first conductivity-type region comprises a first region and a second region, and the anode second conductivity-type region comprises a third region and a fourth region, the dopant concentration of the first region being less than that of the second region, the dopant concentration of the third region being less than that of the fourth region, the third region being provided between the fourth region and a body region, the first region being provided below the fourth region, and the second region being provided below the third region and located between the first region and the body region.
    Type: Application
    Filed: August 26, 2020
    Publication date: November 24, 2022
    Inventors: Long ZHANG, Jie MA, Yan GU, Sen ZHANG, Jing ZHU, Jinli GONG, Weifeng SUN, Longxing SHI
  • Publication number: 20220367716
    Abstract: The present invention discloses a high-threshold power semiconductor device and a manufacturing method thereof. The high-threshold power semiconductor device includes, in sequence from bottom to top: a metal drain electrode, a substrate, a buffer layer, and a drift region; further including: a composite column body which is jointly formed by a drift region protrusion, a columnar p-region and a columnar n-region on the drift region, a channel layer, a passivation layer, a dielectric layer, a heavily doped semiconductor layer, a metal gate electrode and a source metal electrode. The composite column body is formed by sequentially depositing a p-type semiconductor layer and an n-type semiconductor layer on the drift region and then etching same. The channel layer and the passivation layer are formed in sequence by deposition. Thus, the above devices are divided into a cell region and a terminal region.
    Type: Application
    Filed: January 20, 2021
    Publication date: November 17, 2022
    Inventors: Siyang LIU, Weifeng SUN, Chi ZHANG, Shuxuan XIN, Shen LI, Le QIAN, Chen GE, Longxing SHI
  • Publication number: 20220367722
    Abstract: An IGZO thin-film transistor and a method for manufacturing same. The method comprises: acquiring a substrate; forming an IGZO layer on the substrate by means of a solution process; doping V impurities on a surface of the IGZO layer by means of a spin doping process; forming a source electrode at one side of the IGZO layer, and forming a drain electrode at the other side thereof; forming a gate dielectric layer on the doped IGZO layer; and forming a gate electrode on the gate dielectric layer.
    Type: Application
    Filed: August 26, 2020
    Publication date: November 17, 2022
    Inventors: Wangran WU, Guangan YANG, Feng LIN, Guipeng SUN, Yaohui WANG, Weifeng SUN, Longxing SHI
  • Publication number: 20220352369
    Abstract: A laterally double-diffused metal oxide semiconductor device is provided, including: a drift region (3) having a first conductivity type; a first body region (10) disposed on the drift region (3) and having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; a first conductivity type region (13) disposed in the first body region (10); a second body region (12) disposed in the first conductivity type region (13) and having the second conductivity type; a source region (11) disposed in the second body region (12) and having the first conductivity type; and a contact region (9) disposed in the first body region (10) and having the second conductivity type.
    Type: Application
    Filed: August 20, 2020
    Publication date: November 3, 2022
    Applicants: SOUTHEAST UNIVERSITY, CSMC TECHNOLOGIES FAB2 CO.,LTD.
    Inventors: JING ZHU, GUICHUANG ZHU, NAILONG HE, SEN ZHANG, SHAOHONG LI, WEIFENG SUN, LONGXING SHI
  • Patent number: 11394306
    Abstract: Provided is a dynamic control method that turns off a primary-side switching transistor when an output voltage exceeds an upper limit, and control the switching of a secondary-side synchronous rectification transistor with a fixed cycle and a fixed duty cycle. During the time that the synchronous rectification transistor is turned on, the energy of a load capacitor at the output end is extracted to the primary side, which causes the output voltage to drop rapidly and the overshoot voltage to decrease greatly.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: July 19, 2022
    Assignees: CSMC TECHNOLOGIES FAB2 CO., LTD., SOUTHEAST UNIVERSITY
    Inventors: Shen Xu, Wei Wang, Feng Lin, Boyong He, Wei Su, Weifeng Sun, Longxing Shi
  • Publication number: 20220223692
    Abstract: A gallium nitride power device, including: a gallium nitride substrate; cathodes; a plurality of gallium nitride protruding structures arranged on the gallium nitride substrate and between the cathodes, a groove is formed between adjacent gallium nitride protruding structures; an electron transport layer, covering a top portion and side surfaces of each of the gallium nitride protruding structures; a gallium nitride layer, arranged on the electron transport layer and filling each of the grooves; a plurality of second conductivity type regions, where each of the second conductivity type regions extends downward from a top portion of the gallium nitride layer into one of the grooves, and the top portion of each of the gallium nitride protruding structures is higher than a bottom portion of each of the second conductivity type regions; and an anode, arranged on the gallium nitride layer and the second conductivity type regions.
    Type: Application
    Filed: September 25, 2020
    Publication date: July 14, 2022
    Applicants: SOUTHEAST UNIVERSITY, CSMC TECHNOLOGIES FAB2 CO.,LTD
    Inventors: SIYANG LIU, NINGBO LI, DEJIN WANG, KUI XIAO, CHI ZHANG, SHENG LI, XINYI TAO, WEIFENG SUN, LONGXING SHI
  • Patent number: 11367785
    Abstract: A lateral insulated gate bipolar transistor (IGBT) with a low turn-on overshoot current is provided to reduce a peak value of a current flowing through a device during turn-on of a second gate pulse while preventing a current capability and a withstand voltage capability from being degraded. The lateral IGBT includes: a buried oxygen arranged on a P-type substrate, an N-type drift region arranged on the buried oxygen, on which a P-type body region and an N-type buffer region are arranged, a P-type collector region arranged in the N-type buffer region, a field oxide layer arranged above the N-type drift region, a P-type well region arranged in the P-type body region, and a P-type emitter region and an emitter region arranged in the P-type well region, where inner boundaries of the foregoing 4 regions are synchronously recessed to form a pinch-off region. A gate oxide layer is arranged on a surface of the P-type body region, and a polysilicon gate is arranged on the gate oxide layer.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: June 21, 2022
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Jing Zhu, Ankang Li, Long Zhang, Weifeng Sun, Shengli Lu, Longxing Shi
  • Publication number: 20220157975
    Abstract: A lateral insulated gate bipolar transistor (IGBT) with a low turn-on overshoot current is provided to reduce a peak value of a current flowing through a device during turn-on of a second gate pulse while preventing a current capability and a withstand voltage capability from being degraded. The lateral IGBT includes: a buried oxygen arranged on a P-type substrate, an N-type drift region arranged on the buried oxygen, on which a P-type body region and an N-type buffer region are arranged, a P-type collector region arranged in the N-type buffer region, a field oxide layer arranged above the N-type drift region, a P-type well region arranged in the P-type body region, and a P-type emitter region and an emitter region arranged in the P-type well region, where inner boundaries of the foregoing 4 regions are synchronously recessed to form a pinch-off region. A gate oxide layer is arranged on a surface of the P-type body region, and a polysilicon gate is arranged on the gate oxide layer.
    Type: Application
    Filed: March 31, 2020
    Publication date: May 19, 2022
    Inventors: Jing ZHU, Ankang LI, Long ZHANG, Weifeng SUN, Shengli LU, Longxing SHI
  • Patent number: 11336217
    Abstract: A method and an apparatus for reducing noise of a switched reluctance motor, includes: supplying a PWM signal as a driving signal to a driving circuit of a switched reluctance motor; and varying a carrier frequency of the PWM signal as an operation period of the switched reluctance motor varies; if the switched reluctance motor changes phase, determining that the operation period of the switched reluctance motor varies.
    Type: Grant
    Filed: December 29, 2018
    Date of Patent: May 17, 2022
    Assignees: CSMC TECHNOLOGIES FAB2 CO., LTD., SOUTHEAST UNIVERSITY
    Inventors: Rui Zhong, Mingshu Zhang, Sen Zhang, Jinyu Xiao, Wei Su, Weifeng Sun, Longxing Shi
  • Patent number: 11322606
    Abstract: A heterojunction semiconductor device comprises a substrate; a second barrier layer is disposed on the second channel layer and a second channel is formed; a trench gate structure is disposed in the second barrier layer; the trench gate structure is embedded into the second barrier layer and is composed of a gate medium and a gate metal located in the gate medium; an isolation layer is disposed in the second channel layer and separates the second channel layer into an upper layer and a lower layer; a first barrier layer is disposed between the lower layer of the second channel layer and the first channel layer and a first channel is formed; a bottom of the metal drain is flush with a bottom of the first barrier layer; and a first metal source is disposed between the second metal source and the first channel layer.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: May 3, 2022
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Weifeng Sun, Siyang Liu, Sheng Li, Chi Zhang, Xinyi Tao, Ningbo Li, Longxing Shi
  • Patent number: 11323039
    Abstract: A method for improving the conversion efficiency of a CCM mode of a flyback resonant switch power supply, comprising: presetting a critical value Tset, calculating a time interval Ttap between adjacent zero points in the current connection time, outputting a shutdown signal at the zero points, and comparing the time interval Ttap with the preset critical value Tset; when Ttap>Tset, controlling the current shutdown time to be less than the shutdown time of the preceding cycle and outputting a start signal; when Ttap=0, controlling the current shutdown time to be greater than the shutdown time of the preceding cycle and outputting a start signal; and when 0<Ttap<=Tset, controlling the current shutdown time to be the same as the shutdown time of the preceding switch cycle and outputting a start signal.
    Type: Grant
    Filed: December 29, 2018
    Date of Patent: May 3, 2022
    Inventors: Weifeng Sun, Rongrong Tao, Hao Wang, Jinyu Xiao, Wei Su, Shen Xu, Longxing Shi