Abstract: The present invention relates to the field of IPC C08L69, and more specifically relates to a chemical-resistant polycarbonate composition and a preparation method therefor. The composition includes 15-30 parts of a polycarbonate-polysiloxane copolymer, 50-90 parts of a bisphenol A polycarbonate, 20-40 parts of a polycarbonate master batch, and 0.01-0.1 part of an additive; and the composition includes the polycarbonate-polysiloxane copolymer having a ratio of a polysiloxane block of 15-30 wt %. By adding an organic silicon composition SFR 100, a polycarbonate material can be obviously improved in resistance to corrosion of chemical agents without cracking, which can be applied to medical treatment and electronic equipment. An E value (polymerization unit) is 40-100, and a proportion of the polycarbonate-polysiloxane copolymer in the composition is greater than 17.

Abstract: The present invention provides a double-crosslinked fibrin gel, which is a solid hydrogel composed of a network structure with a blocking function and a network structure with an adhesion function, where the network structure with the blocking function is a three-dimensional fibrin network, and the network structure with the adhesion function is a three-dimensional photosensitive gel network; each channel of the photosensitive gel network has a group of the fibrin network inside, and each group of the fibrin network has overall continuity; on the whole, the three-dimensional fibrin network disperses disorderly throughout a surface and an interior of the solid hydrogel. The present invention further provides a raw material composition, a kit for preparing the double-crosslinked fibrin gel, and an application of the kit to prepare an in-situ rapid clotting and hemostatic material.

Abstract: A method of preparing a polyamide composite membrane using a vapor-assisted electrostatic spray is provided which relates to the field of preparation of polyamide composite membranes and comprises: step S1, adjusting a relative humidity of a surrounding environment of an electrostatic spray equipment to 80% to 90%; step S2, taking an amine monomer solution and an acyl chloride monomer solution as raw materials and placing the two raw materials in a spray system of the electrostatic spray equipment; step S3, wrapping a polymer ultrafiltration membrane on a receiving roller of the electrostatic spray equipment and setting electrostatic spray process parameters for electrostatic spraying; step S4, taking down an electrostatically-sprayed composite polymer membrane and placing the composite polymer membrane in an environment of 50 to 80° C. for heat treatment of 5 to 20 minutes, to prepare a finished polyamide composite membrane.

Abstract: This application provides an adhesive film and a preparation method thereof, a composite assembly, and an electronic device. The adhesive film is prepared through a cross-linking reaction of a prepolymer. The prepolymer includes an alkyl acrylate soft monomer and an acrylate polar monomer. A mass fraction of the alkyl acrylate soft monomer in the prepolymer is greater than or equal to 60 wt %. A mass fraction of the acrylate polar monomer in the prepolymer is less than 30 wt %. The adhesive film provided in this application has an excellent low modulus at a low temperature and a high creep recovery rate, and can be used to improve a service life of a foldable electronic device in repeated folding processes.

Abstract: The present invention discloses a centrifugal spinning apparatus, including a frame, a spinning device, a feeding device for providing a spinning solution to the spinning device, and a collection device for collecting centrifugal spinning fibers ejected by the spinning device. The collection device is horizontally disposed below the spinning device, to enable the centrifugal spinning fibers ejected by the spinning device to be attached to a surface of the collection device. A planar receiving-type centrifugal spinning automatic production device using the centrifugal spinning apparatus breaks through existing centrifugal spinning based on ring collection and centrifugal spinning technologies based on electrostatic collection, resolves a preparation problem of continuous filament of the centrifugal spinning, and achieves mass production of the centrifugal spinning. The whole production process is completed automatically without manual intervention.

Abstract: The present disclosure provides a power battery monitoring system and a method. The system includes a battery assembly, N monitoring assemblies and an upper monitoring platform. The N monitoring assemblies are connected in series with each other, and a first monitoring assembly is connected with the upper monitoring platform, wherein the number of sampling channels of each monitoring assembly is M. The power battery monitoring system can segment the battery cells; the number of the battery cells in each segment is M; the battery cells in each segment are connected with a same monitoring assembly; and the N monitoring assemblies acquire sampling data of the battery cells in this segment through the corresponding sampling channel, so as to realize the monitoring of the battery cells in this segment by the upper monitoring platform.

Abstract: A technology flushing a hierarchical cache structure based on a designated key identification code and a designated address. A processor includes a first core and a last level cache (LLC). The first core includes a decoder, a memory ordering buffer, and a first in-core cache module. In response to an Instruction Set Architecture (ISA) instruction that requests to flush a hierarchical cache structure according to a designated key identification code and a designated address, the decoder outputs at least one microinstruction. According to the at least one microinstruction, a flushing request with the designated key identification code and the designated address is provided to the first in-core cache module through the memory ordering buffer, and then the first in-core cache module provides the LLC with the flushing request, so that the LLC flushes its matching cache line which matches the designated key identification code and the designated address.

Abstract: A processor and a method for designating an in-core cache of a hierarchical cache system to perform writing-back and invalidation of cached data are shown. In response to an instruction that is in the instruction set architecture and is executed to designate a designated-level cache within the current core as a target to perform writing-back and invalidation, a decoder of the current core outputs microinstructions. According to the microinstructions, a level-designation request indicating the designated-level cache within the current core is transferred to the hierarchical cache system through the memory order buffer. In response to the level-designation request, the hierarchical cache system recognizes cache lines related to the designated-level cache of the current core, writes modified cache lines (which are obtained from the recognized cache lines) back to the system memory, and then invalidates all the recognized cache lines from the hierarchical cache system.

Abstract: A battery pack detection connection apparatus includes: a communication module used for communicating with a vehicle communication interface and a battery pack; a microcontroller unit used for extracting change features of an externally inputted signal, performing signal feature reconstruction on the extracted change features of the signal, and transmitting the reconstructed signal features to a function generator or signal module; at least one function generator used for outputting, according to the reconstructed signal features, a first-type waveform signal exchanged between a vehicle and the battery pack; and the signal module used for outputting, according to the reconstructed signal features, a second-type waveform signal exchanged between the vehicle and the battery pack. The present apparatus uses the function generator and the signal module to achieve signals required by the battery pack for interaction. The same hardware can be used to match different brands of vehicle models.

Abstract: A battery equalization method, comprising: step A1: according to acquired data information of a battery, determining that the battery is a balanceable battery or a replaceable battery; step A2: charging and discharging a module in the balanceable battery; step A3: monitoring the voltage of each cell in the module and the temperature of the module; and step A4: shunting the equalization current between the cells, so as to ensure that the voltage difference between the cells does not exceed a first preset voltage difference value. Further disclosed is a battery equalization system. By means of the method, a battery can be effectively discriminated, thereby improving the equalization effect, shortening the equalization time, and thus improving the equalization efficiency.

Abstract: A computing system with a first instruction of an instruction set architecture (ISA) for direct invalidation, without writing back, in a hierarchical cache structure based on one single designated key identification code, and a second instruction of ISA for direct invalidation, without writing back, in the hierarchical cache structure based on a plurality of designated key identification codes is shown. A decoder transforms the first or second instruction into at least one microinstruction. Based on the at least one microinstruction, one direct invalidation request is provided corresponding to each designated key identification code, to be passed to the hierarchical cache structure through a memory ordering buffer. For each direct invalidation request, the cache line write-back and invalidation regarding a designated key identification code is performed on a last-level cache first, and then is performed on the in-core cache modules.

Abstract: A processor and a method for designating a demotion target to demote the demotion target from an in-core cache structure to an out-of-core cache structure is shown. In response to a cache data demotion instruction supported by an instruction set architecture, a first core of a processor operates a decoder to decode the cache data demotion instruction into microinstructions. According to the microinstructions, a demotion target designation request is transferred to a last-level cache (LLC) through a memory order buffer to drive the LLC to query an out-of-core cache table. According to the demotion target's cache status in the first core obtained from the out-of-core cache table, the LLC outputs a snoop request to the first core to snoop on the demotion target and demote the demotion target from the in-core cache structure of the first core to the LLC.

Abstract: An instruction execution method for a microprocessor is provided. The microprocessor includes a model specific register (MSR). And, the instruction execution method includes the following steps. A target instruction is received using an instruction cache. The target instruction is decoded using an instruction translator to determine whether the target instruction is a specific instruction is a specific instruction. When the target instruction is the specific instruction, a model specific register index of the target instruction is obtained to directly read or write the model specific register.

Abstract: An instruction configuration and execution method includes the following steps. A target instruction is received through an instruction cache. The target instruction is decoded by an instruction translator. It is determined whether the target instruction has the authority to read or write the model specific register in an unprivileged state. It is determined whether the model specific register index of the specific instruction corresponds to a specific model specific register, so as to order the microprocessor to perform an instruction serialization operation.

Abstract: A computer-implemented method for generating an improved map of field anomalies using digital images and machine learning models is disclosed.

Abstract: A interconnect system, including a plurality of sockets and a first interconnect interface. Any two of the sockets are accessible to each other's hardware resources by transmitting a first packet and a second packet through the first interconnect interface. The first packet includes first interconnect information, used for establishing communication between the two sockets. The second packet includes a first data payload, loaded from one of the two sockets. The sockets include a first socket and a second socket, configured to be interconnected with each other through the first interconnect interface.

Abstract: A method for executing new instructions is provided. The method is used in a processor and includes: receiving an instruction; when the received instruction is an unknown instruction, executing a conversion program by an operating system, wherein the conversion program executes the following steps: determining whether the received instruction is a new instruction; converting the received instruction into at least one old instruction when the received instruction is a new instruction; and executing the at least one old instruction.

Abstract: The present invention discloses a permanent packer and an extended gas lift method using the permanent packer, the method comprising: S1. imbedding the extended gas lift embedded pipe when setting the permanent packer, wherein the extended gas lift embedded pipe has an upper end being closed and a lower end being open, is provided therein with a one-way valve through which the fluid can pass from top to bottom; S2. lowering a breaking device from the production casing when in the extended gas lift, to break the upper end of the extended gas lift embedded pipe such that the upper and lower ends of the extended gas lift embedded pipe are communicated; and S3. injecting gas into the production casing, lifting the accumulated liquid in the bottom hole to the ground surface, to complete the extended gas lift.

Abstract: A computing system with a first instruction of an instruction set architecture (ISA) for write-back and invalidation in a hierarchical cache structure based on one single designated key identification code, and a second instruction of ISA for write-back and invalidation in the hierarchical cache structure based on a plurality of designated key identification codes is shown. A decoder transforms the first or second instruction into at least one microinstruction. Based on the at least one microinstruction, one write-back and invalidation request is provided corresponding to each designated key identification code, to be passed to the hierarchical cache structure through a memory ordering buffer. For each write-back and invalidation request, the cache line write-back and invalidation regarding a designated key identification code is performed on a last-level cache first, and then is performed on the in-core cache modules.

Abstract: A technology for flushing a translation lookaside buffer (TLB) according to a designated key identification code (designated key ID). An instruction of an instruction set architecture is proposed to flush the TLB according to the designated key ID. A decoder transforms the instruction into at least one microinstruction. According to a flushing microinstruction included in the at least one microinstruction, a designated key ID is supplied to a control logic circuit of the TLB through a memory order buffer, so that the control logic circuit flushes matched entries in the TLB, wherein the matched entries match the designated key ID.