Patents by Inventor Weimin Zeng

Weimin Zeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140187626
    Abstract: The present invention relates to chemical entities originated from natural sources and further synthesized for therapeutic uses. More particularly, the present invention relates to norcantharidin analogues synthesized by a transition metal-catalyzed alkynylation of oxanorbornadiene derivatives and their antitumor effects.
    Type: Application
    Filed: December 16, 2013
    Publication date: July 3, 2014
    Applicant: Hong Kong Baptist University
    Inventors: Zhaoxiang BIAN, Chengyuan LIN, Baomin FAN, Huaixue MU, Yongyun ZHOU, Weimin ZENG, Aiping LU, Albert Sun Chi CHAN
  • Patent number: 8101525
    Abstract: Methods for fabricating a semiconductor device having a lanthanum-family-based oxide layer are described. A gate stack having a lanthanum-family-based oxide layer is provided above a substrate. At least a portion of the lanthanum-family-based oxide layer is modified to form a lanthanum-family-based halide portion. The lanthanum-family-based halide portion is removed with a water vapor treatment.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: January 24, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Meihua Shen, Noel Sun, Nicolas Gani, Han-Hsiang Chen, Eric Pei, Weimin Zeng, Thorsten B. Lill, Uday Mitra, Ellie Y. Yieh
  • Publication number: 20100210112
    Abstract: Methods for fabricating a semiconductor device having a lanthanum-family-based oxide layer are described. A gate stack having a lanthanum-family-based oxide layer is provided above a substrate. At least a portion of the lanthanum-family-based oxide layer is modified to form a lanthanum-family-based halide portion. The lanthanum-family-based halide portion is removed with a water vapor treatment.
    Type: Application
    Filed: February 13, 2009
    Publication date: August 19, 2010
    Applicant: Applied Materials, Inc.
    Inventors: Meihua Shen, Noel Sun, Nicolas Gani, Han-Hsiang Chen, Eric Pei, Weimin Zeng, Thorsten B. Lill, Uday Mitra, Ellie Y. Yieh
  • Publication number: 20090003451
    Abstract: A shared pipeline architecture is provided for H.264 motion vector prediction and residual decoding, and intra prediction for CABAC and CALVC entropy in Main Profile and High Profile for standard and high definition applications. All motion vector predictions and residual decoding of I-type, P-type, and B-type pictures are completed through the shared pipeline. The architecture enables better performance and uses less memory than conventional architectures. The architecture can be completely implemented in hardware as a system-on-chip or chip set using, for example, field programmable gate array (FPGA) technology or application specific integrated circuitry (ASIC) or other custom-built logic.
    Type: Application
    Filed: August 20, 2008
    Publication date: January 1, 2009
    Applicant: MICRONAS USA, INC.
    Inventors: Teng Chiang Lin, Weimin Zeng
  • Patent number: 7430238
    Abstract: A shared pipeline architecture is provided for H.264 motion vector prediction and residual decoding, and intra prediction for CABAC and CALVC entropy in Main Profile and High Profile for standard and high definition applications. All motion vector predictions and residual decoding of I-type, P-type, and B-type pictures are completed through the shared pipeline. The architecture enables better performance and uses less memory than conventional architectures. The architecture can be completely implemented in hardware as a system-on-chip or chip set using, for example, field programmable gate array (FPGA) technology or application specific integrated circuitry (ASIC) or other custom-built logic.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: September 30, 2008
    Assignee: Micronas USA, Inc.
    Inventors: Teng Chiang Lin, Weimin Zeng
  • Patent number: 7366238
    Abstract: A noise filter for a video processing system includes a block selector, a cost calculator, a cost table, a cost comparator, and a coefficient filter. The block selector is coupled to receive data from the quantization unit and selects blocks for additional filtering. The selected blocks are provided to the cost calculator determines a cost for each of the coefficients in the block using the cost table and the costs are summed. The cost comparator compares the total to a threshold, and filters the coefficients using the coefficient filter if the total is greater a preset threshold. The noise filter to the VLC unit then outputs the filter data.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: April 29, 2008
    Assignee: Micronas USA, Inc.
    Inventors: Weimin Zeng, Li Sha, Ping Zhu
  • Publication number: 20080077905
    Abstract: A design technique is disclosed that allows video processing hardware designers to effectively employ the requirements of a video processing standard (e.g., H.264 specification or other such standard) during the hardware architecture design phase of the design process. The technique eliminates or otherwise reduces costly multiple passes through the resource intensive implementation and verification portions of the design process, and allows designers to make changes to the hardware architecture design, thereby ensuring verification at the implementation phase.
    Type: Application
    Filed: November 19, 2007
    Publication date: March 27, 2008
    Inventors: Li SHA, Weimin Zeng
  • Patent number: 7310785
    Abstract: A design technique is disclosed that allows video processing hardware designers to effectively employ the requirements of a video processing standard (e.g., H.264 specification or other such standard) during the hardware architecture design phase of the design process. The technique eliminates or otherwise reduces costly multiple passes through the resource intensive implementation and verification portions of the design process, and allows designers to make changes to the hardware architecture design, thereby ensuring verification at the implementation phase.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: December 18, 2007
    Assignee: Micronas USA, Inc.
    Inventors: Li Sha, Weimin Zeng
  • Patent number: 7085320
    Abstract: A video compression scheme enables the user to select one of many video compression formats, including the widely-used standard video formats such as MPEG-1, MPEG-2, MPEG-4 and H.263. In one embodiment, the scheme is implemented as a hardware-software combination, with the hardware portion, preferably implemented as an ASIC chip, performing the core compression and the software portion dealing with the detailed formatting. In another embodiment, a 32-bit aligned transitional data format is used.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: August 1, 2006
    Assignee: WIS Technologies, Inc.
    Inventors: He Ouyang, Li Sha, Shuhua Xiang, Yaojun Luo, Weimin Zeng, Jun Ding
  • Publication number: 20060143588
    Abstract: A design technique is disclosed that allows video processing hardware designers to effectively employ the requirements of a video processing standard (e.g., H.264 specification or other such standard) during the hardware architecture design phase of the design process. The technique eliminates or otherwise reduces costly multiple passes through the resource intensive implementation and verification portions of the design process, and allows designers to make changes to the hardware architecture design, thereby ensuring verification at the implementation phase.
    Type: Application
    Filed: April 13, 2005
    Publication date: June 29, 2006
    Inventors: Li Sha, Weimin Zeng
  • Publication number: 20060126725
    Abstract: According to one embodiment, the present invention generates a test vector for verification of a video encoder or decoder by encoding video data using a permissible combination of parameters. One embodiment of the present invention provides for verification of a video decoder by performing at least one video decoding operation and comparing a resulting partially or fully decoded test vector to an expected value. Another embodiment of the present invention provides for verification of a video encoder by performing at least one video encoding operation using a selected combination of parameters, and comparing a resulting partially or fully encoded test vector to an expected value.
    Type: Application
    Filed: May 5, 2005
    Publication date: June 15, 2006
    Inventors: Weimin Zeng, Yaojun Luo, Yu Tian
  • Publication number: 20060126726
    Abstract: In one embodiment, a DSP structure includes four main sections: DEQ, IDCT for row, IDCT for column, and motion compensation. The data input sequence is organized in such a way to facilitate the data loading into hardware structures for row IDCT and column IDCT. Two types of decoding flows are enabled by the DSP structure: H.264 decoding flows (e.g., dequantization, inverse discrete Hadamard transform, intra prediction, and motion decompensation), and non-H.264 decoding flows (e.g., dequantization, row inverse discrete cosine transformation, column inverse discrete cosine transformation, and motion decompensation). The non-H.264 decoding flow can be used for standards such as MPEG1/2/4, H.263, Microsoft WMV9, and Sony Digital Video.
    Type: Application
    Filed: May 25, 2005
    Publication date: June 15, 2006
    Inventors: Teng Lin, Hongjun Yuan, Weimin Zeng, Liang Peng
  • Publication number: 20060126740
    Abstract: A shared pipeline architecture is provided for H.264 motion vector prediction and residual decoding, and intra prediction for CABAC and CALVC entropy in Main Profile and High Profile for standard and high definition applications. All motion vector predictions and residual decoding of I-type, P-type, and B-type pictures are completed through the shared pipeline. The architecture enables better performance and uses less memory than conventional architectures. The architecture can be completely implemented in hardware as a system-on-chip or chip set using, for example, field programmable gate array (FPGA) technology or application specific integrated circuitry (ASIC) or other custom-built logic.
    Type: Application
    Filed: May 25, 2005
    Publication date: June 15, 2006
    Inventors: Teng Lin, Weimin Zeng
  • Publication number: 20050249293
    Abstract: A noise filter for a video processing system includes a block selector, a cost calculator, a cost table, a cost comparator, and a coefficient filter. The block selector is coupled to receive data from the quantization unit and selects blocks for additional filtering. The selected blocks are provided to the cost calculator determines a cost for each of the coefficients in the block using the cost table and the costs are summed. The cost comparator compares the total to a threshold, and filters the coefficients using the coefficient filter if the total is greater a preset threshold. The noise filter to the VLC unit then outputs the filter data.
    Type: Application
    Filed: October 5, 2004
    Publication date: November 10, 2005
    Inventors: Weimin Zeng, Li Alpha, Ping Zhu
  • Publication number: 20050226324
    Abstract: A video compression scheme enables the user to select one of many video compression formats, including the widely-used standard video formats such as MPEG-1, MPEG-2, MPEG-4 and H.263. In one embodiment, the scheme is implemented as a hardware-software combination, with the hardware portion, preferably implemented as an ASIC chip, performing the core compression and the software portion dealing with the detailed formatting. In another embodiment, a 32-bit aligned transitional data format is used.
    Type: Application
    Filed: September 14, 2001
    Publication date: October 13, 2005
    Inventors: He Ouyang, Li Sha, Shuhua Xiang, Yaojun Luo, Weimin Zeng, Jun Ding
  • Publication number: 20050207663
    Abstract: The invention relates generally to compression of video data and specifically to lowering at least a cost of motion information while encoding a macroblock. According to one embodiment, the present invention searches for a matching block that lowers a cost of encoding the macroblock including the cost of encoding motion information. According to another embodiment, the present invention lowers the cost of encoding the macroblock including the cost of encoding motion information at one or more stages of a multiresolution search.
    Type: Application
    Filed: February 23, 2005
    Publication date: September 22, 2005
    Inventors: Weimin Zeng, Li Sha, Ping Zhu