Patents by Inventor Wei-Ming Chen

Wei-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260115722
    Abstract: A pressure generating device includes a tank, a deformable membrane, a driving device, and a connection unit. The tank defines a chamber therein, and includes an opening and a communication port each of which is in fluid communication with the chamber. The deformable membrane is disposed to seal the opening. The driving device includes a driving shaft having an end which confronts the deformable membrane. The connection unit is configured to couple the driving shaft with the deformable membrane and to permit the deformable membrane to be driven by the driving shaft to transform between a flat state and a deformed state. A detecting system including the pressure generating device for detecting quality of a test sample is also provided.
    Type: Application
    Filed: October 25, 2024
    Publication date: April 30, 2026
    Inventors: Wei-Ming CHEN, I-Chiao HSIEH, Yung-Hsiang LIN, Chien-Hung CHEN
  • Publication number: 20260111643
    Abstract: The present disclosure provides a method and a non-transitory computer-readable medium for arranging components within a semiconductor device. The method includes providing a plurality of electrical components in a pre-layout, generating a first layout by routing the plurality of electrical components, obtaining a first resistance between a power terminal of the first layout and a first terminal of a first electrical component in the first layout, comparing the first resistance and a first threshold, adjusting routing of the first layout such that the first resistance is less than the first threshold, and generating a tape out file for the semiconductor device according to the first layout.
    Type: Application
    Filed: December 18, 2025
    Publication date: April 23, 2026
    Inventors: HSIEN YU TSENG, WEI-MING CHEN
  • Patent number: 12599904
    Abstract: A pressure generating device includes a tank, a deformable membrane, a driving device, and an actuating arm. The tank defines a chamber therein, and includes an opening and a communication port each of which is in fluid communication with the chamber. The deformable membrane is disposed to seal the opening, and is deformable between a flat state and a deformed state. The actuating arm is coupled to be driven by the driving device to move between a first position, where the deformable membrane is in the flat state, and a second position, where the deformable membrane is forced to be in the deformed state, such that a predetermined negative pressure is generated through the communication port when the actuating arm is driven from one of the first and second positions to the other one of the first and second positions.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: April 14, 2026
    Assignee: INTI TAIWAN, INC.
    Inventors: Wei-Ming Chen, Ching-Yi Mao
  • Patent number: 12530516
    Abstract: The present disclosure provides a method and a non-transitory computer-readable medium for arranging components within a semiconductor device. The method includes providing a plurality of electrical components in a pre-layout, generating a first layout by routing the plurality of electrical components, obtaining a first resistance between a power terminal of the first layout and a first terminal of a first electrical component in the first layout, comparing the first resistance and a first threshold, adjusting routing of the first layout such that the first resistance is less than the first threshold, and generating a tape out file for the semiconductor device according to the first layout.
    Type: Grant
    Filed: August 3, 2022
    Date of Patent: January 20, 2026
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsien Yu Tseng, Wei-Ming Chen
  • Patent number: 12498020
    Abstract: A conjugate cam reducer includes input and output units disposed at two opposite sides of a transmission unit along an output axis. The transmission unit includes input-side and output-side cam discs having first and second grooved surfaces. The input unit includes an input disc having a plurality of first receiving grooves registered with the first grooved surfaces to receive input rollers, and an eccentric shaft rotated to drive rotation of the transmission unit in an eccentric cam motion. The output unit includes an output disc having an inner peripheral wall which engages with the output-side cam disc, and a plurality of second receiving grooves which are registered with the second grooves to receive output rollers. An outer diameter of each first toothed surface and an outer diameter of each second toothed surface is gradually increased along a direction parallel to the output axis.
    Type: Grant
    Filed: November 13, 2024
    Date of Patent: December 16, 2025
    Assignee: National Sun Yat-Sen University
    Inventors: Der-Min Tsay, Kun-Lung Hsu, Wei-Ming Chen, Jyun-Ting Chen, Yuan-Shin Lin
  • Publication number: 20250362338
    Abstract: A method includes identifying a structure of interest in an IC design; assigning a thermal affected zone to a region of the IC design encompassing at least a portion of the structure of interest; identifying a plurality of structures that are, in whole or in part, in the thermal affected zone and that correspond to IC device elements that self-heat during operation of an IC device that is based on the IC design; modeling a corresponding plurality of operating temperatures for the plurality of structures and identifying, among the plurality of operating temperatures, a highest temperature; identifying, among the plurality of structures, a structure having the highest temperature as a first neighboring structure; assigning a rating factor based on a distance between the structure of interest and the first neighboring structure; and modeling an operating temperature of the structure of interest based on the highest temperature and the rating factor.
    Type: Application
    Filed: May 23, 2024
    Publication date: November 27, 2025
    Inventors: Chun-Wei CHANG, Wei-Ming CHEN, Hsien YU TSENG, Ming-Hong HSIEH
  • Publication number: 20250322139
    Abstract: The present disclosure provides a method for evaluating temperature information of an integrated circuit. The method includes the following steps: identifying an active region in an integrated circuit design layout; dividing the active region into a plurality of segments, wherein each segment comprises a plurality of conductors formed thereon; determining a weight of each conductor with respect to each segment; calculating a self-heat temperature increase of each conductor; and calculating a temperature increase of each segment using the weight and the self-heat temperature increase of each conductor within a valid heat-effective region of each segment.
    Type: Application
    Filed: April 11, 2024
    Publication date: October 16, 2025
    Inventors: CHUN-WEI CHANG, HSIEN YU TSENG, WEI-MING CHEN, MING-WEN LIN
  • Publication number: 20250257392
    Abstract: The disclosure relates to a kit for determining an endometrial status and a method of determining a miRNA expression profile of an endometrial sample. The kit comprises: (a) one or more microRNA (miRNA) profiling chips targeting a plurality of miRNAs, and (b) instructions on (i) determining a miRNA expression profile of an endometrial sample from a woman, using the one or more miRNA profiling chips, and (ii) obtaining a receptivity predictive score based on the miRNA expression profile, using a computer-based algorithm, wherein the plurality of miRNAs comprise at least 167 miRNA s having the sequences of SEQ ID NOs: 1-167, respectively.
    Type: Application
    Filed: April 22, 2025
    Publication date: August 14, 2025
    Applicant: Inti Taiwan, Inc.
    Inventors: Shih-Ting Kang, Wei-Ming Chen
  • Publication number: 20250252071
    Abstract: An electronic system and an operating method for the electronic system are provided. The electronic system includes a programmable circuit, a memory circuit, a controller, and a switching circuit. The controller provides a first control signal. The switching circuit has a control terminal, a first terminal, a second terminal, and a third terminal. The first terminal is coupled to the programmable circuit. The second terminal is coupled to the memory circuit. The control terminal and the third terminal are coupled to the controller. The switching circuit receives the first control signal through the control terminal to connect the third terminal to the second terminal, so that update data is stored into the memory circuit.
    Type: Application
    Filed: September 26, 2024
    Publication date: August 7, 2025
    Applicant: PEGATRON CORPORATION
    Inventors: Cong-Feng Wei, Wei-Ming Chen, Yu-Shu Yeh
  • Publication number: 20250252244
    Abstract: The present disclosure provides a method and a non-transitory computer readable media for inter-metal dielectric reliability check. The method comprises: receiving an electronic layout, the electronic layout including a first plurality of electrical components in a first layer; determining an internal voltage difference within each electrical component in the first layer based on parasitic effect; generating a simulation voltage value for each electrical component in the first layer based on the internal voltage differences; and tagging a pair of electrical components in the first layer when a first voltage difference between the pair of electrical components exceeds a first voltage threshold. The first voltage difference is determined based on the simulation voltage value of each electrical component.
    Type: Application
    Filed: April 24, 2025
    Publication date: August 7, 2025
    Inventors: HSIEN YU TSENG, WEI-MING CHEN
  • Patent number: 12354267
    Abstract: The present disclosure generally relates to systems and methods for evaluating viability of oocytes. In some implementation examples, an image sequence associated with an oocyte being aspirated into a pressure tool is obtained. Using a segmentation model, objects associated with the oocyte can be identified. Based on the objects identified, features such as morphological features and an aspiration depth associated with the oocyte can be determined. At least some of the features can then be fed into a machine learning model to generate an oocyte grade that indicates a likelihood of the oocyte developing into a usable blastocyst. Optionally, the oocyte grade can be presented to a user via an interactive user interface.
    Type: Grant
    Filed: October 2, 2024
    Date of Patent: July 8, 2025
    Assignee: Inti Taiwan, Inc.
    Inventors: Wei-Ming Chen, I-Chiao Hsieh, Chung-Li Chiang
  • Patent number: 12314652
    Abstract: The present disclosure provides a method and a non-transitory computer readable media for inter-metal dielectric reliability check. The method comprises: receiving an electronic layout, the electronic layout including a first plurality of electrical components in a first layer; determining an internal voltage difference within each electrical component in the first layer based on parasitic effect; generating a simulation voltage value for each electrical component in the first layer based on the internal voltage differences; and tagging a pair of electrical components in the first layer when a first voltage difference between the pair of electrical components exceeds a first voltage threshold. The first voltage difference is determined based on the simulation voltage value of each electrical component.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: May 27, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsien Yu Tseng, Wei-Ming Chen
  • Patent number: 12265773
    Abstract: The present disclosure provides a method and an apparatus for testing a semiconductor device. The method includes providing an active area in an integrated circuit design layout; grouping the active area into a first region and a second region; calculating a first self-heating temperature of the first region of the active area; calculating a second self-heating temperature of the second region of the active area; and determining an Electromigration (EM) evaluation based on the first self-heating temperature and the second self-heating temperature.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: April 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsien Yu Tseng, Wei-Ming Chen
  • Publication number: 20250067321
    Abstract: A conjugate cam reducer includes input and output units disposed at two opposite sides of a transmission unit along an output axis. The transmission unit includes input-side and output-side cam discs having first and second grooved surfaces. The input unit includes an input disc having a plurality of first receiving grooves registered with the first grooved surfaces to receive input rollers, and an eccentric shaft rotated to drive rotation of the transmission unit in an eccentric cam motion. The output unit includes an output disc having an inner peripheral wall which engages with the output-side cam disc, and a plurality of second receiving grooves which are registered with the second grooves to receive output rollers. An outer diameter of each first toothed surface and an outer diameter of each second toothed surface is gradually increased along a direction parallel to the output axis.
    Type: Application
    Filed: November 13, 2024
    Publication date: February 27, 2025
    Applicant: National Sun Yat-Sen University
    Inventors: Der-Min TSAY, Kun-Lung HSU, Wei-Ming CHEN, Jyun-Ting CHEN, Yuan-Shin LIN
  • Publication number: 20240386179
    Abstract: The present disclosure provides a method and an apparatus for testing a semiconductor device. The method includes providing an active area in an integrated circuit design layout; grouping the active area into a plurality of regions, each of the regions including at least one polysilicon gate; calculating an operating temperature of the at least one polysilicon gate in each of the regions; calculating a self-heating temperature of each of the regions based on the operating temperature of the at least one polysilicon gate in each of the regions; determining an Electromigration (EM) evaluation based on the self-heating temperatures of the regions; and generating a semiconductor device based on the integrated circuit design layout passing the EM evaluation, wherein one of the regions includes a number of polysilicon gates disposed thereon different from the number of polysilicon gates disposed on the rest of regions.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: HSIEN YU TSENG, WEI-MING CHEN
  • Publication number: 20240370631
    Abstract: A system including computer readable storage media including executable instructions and one or more processors configured to execute the executable instructions to obtain a schematic netlist and a performance specification for an integrated circuit, determine electrical constraints for nets in the schematic netlist based on the performance specification, determine physical constraints from the electrical constraints, rout the nets in the schematic netlist based on the electrical constraints and the physical constraints, and provide a data file of a layout.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Hsien Yu Tseng, Guan-Ruei Lu, Wei-Ming Chen, Chih.Chi. Hsiao
  • Publication number: 20240351035
    Abstract: A pressure generating device includes a tank, a deformable membrane, a driving device, and an actuating arm. The tank defines a chamber therein, and includes an opening and a communication port each of which is in fluid communication with the chamber. The deformable membrane is disposed to seal the opening, and is deformable between a flat state and a deformed state. The actuating arm is coupled to be driven by the driving device to move between a first position, where the deformable membrane is in the flat state, and a second position, where the deformable membrane is forced to be in the deformed state, such that a predetermined negative pressure is generated through the communication port when the actuating arm is driven from one of the first and second positions to the other one of the first and second positions.
    Type: Application
    Filed: April 24, 2023
    Publication date: October 24, 2024
    Inventors: Wei-Ming CHEN, Ching-Yi MAO
  • Publication number: 20240309442
    Abstract: The disclosure relates to methods for determining an endometrial status using a sample, for example, an endometrial biopsy, from a woman, comprising: (a) performing an assay on the endometrial sample from the woman to determine a microRNA (miRNA) expression profile of the endometrial sample, wherein the miRNA expression profile comprises expression levels of a plurality of miRNAs, for example, 167 miRNAs having the sequences of SEQ ID NOs:1-167, respectively; and (b) analyzing the miRNA expression profile to obtain a receptivity predictive score using, for example, a computer-based algorithm. Aspects of the disclosure further relate to kits suitable for performing the methods, as well as uses of the kits for diagnostic and therapeutic purposes.
    Type: Application
    Filed: June 5, 2024
    Publication date: September 19, 2024
    Applicant: Inti Taiwan, Inc.
    Inventors: Shih-Ting Kang, Wei-Ming Chen
  • Patent number: 12086525
    Abstract: A system including computer readable storage media including executable instructions and one or more processors configured to execute the executable instructions to obtain a schematic netlist and a performance specification for an integrated circuit, determine electrical constraints for nets in the schematic netlist based on the performance specification, determine physical constraints from the electrical constraints, rout the nets in the schematic netlist based on the electrical constraints and the physical constraints, and provide a data file of a layout.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien Yu Tseng, Guan-Ruei Lu, Wei-Ming Chen, Chih.Chi. Hsiao
  • Patent number: 12020782
    Abstract: The present disclosure generally relates to systems and methods for evaluating viability of oocytes. In some implementation examples, an image sequence associated with an oocyte being aspirated into a pressure tool is obtained. Based on the image sequence and pressures applied on the oocyte, morphological features and mechanical features associated with the oocyte can be derived. At least some of the features can then be fed into a machine learning model to determine metrics indicative of quality of the oocyte, where a particular metric may be indicative of blastocyst formation. Optionally, the determined oocyte quality information can be presented to a user via an interactive user interface.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: June 25, 2024
    Assignee: Inti Taiwan, Inc.
    Inventors: Wei-Ming Chen, I-Chiao Hsieh, Chung-Li Chiang