Patents by Inventor Weirong Zhu
Weirong Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250094195Abstract: A resource management configuration may receive an API request from an API server. The API request specifies task information from a plurality of tenants. The configuration transmits status information of a plurality of VMs to the API server to assign tasks to one or more VMs based on the task information and the status information. Tasks assigned to a VM of the plurality of VMs are for one tenant of the plurality of tenants. The configuration configures on an untrusted network, network security groups for managing communications of tenants such that a network security group configured for a tenant permits communications between VMs assigned to the same tenant but prevents communications between VMs assigned to different tenants. The configuration pins each assigned VM of the one or more assigned VMs to perform the task based on the task information of the corresponding tenant.Type: ApplicationFiled: September 15, 2023Publication date: March 20, 2025Inventors: Aaron Daniel Davidson, Thomas Garnier, Lin Guo, Zhe He, Manlin Li, Yang Liu, Feng Wang, Hong Zhang, Weirong Zhu
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Patent number: 12202760Abstract: The present application provides a glass fiber nozzle structure, bushing and production device. The glass fiber nozzle structure includes a nozzle body and a hole provided on the nozzle body. The hole includes an upper hole portion and a lower hole portion communicated with the upper hole portion and located below the upper hole portion. The lower hole portion has an elongated cross-section. A projection of the lower hole portion is located within a projection of the upper hole portion in a projection on a plane perpendicular to an axis line of the lower hole portion. A length and a width of the lower hole portion have a ratio of 5:1 to 12:1. The glass fiber nozzle of the present application has a simple structure and a long service cycle, and an aspect ratio of flat glass fibers produced by the nozzle structure is maintained between 2.7 and 4.2, thereby effectively improving performance of the flat glass fibers.Type: GrantFiled: December 10, 2021Date of Patent: January 21, 2025Assignee: JUSHI GROUP CO., LTD.Inventors: Guorong Cao, Weirong Ma, Zhangbin Zhu, Qixin Zhu, Xuming Shen, Haixing Wang
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Patent number: 10620916Abstract: A high level programming language provides a read-only communication operator that prevents a computational space from being written. An indexable type with a rank and element type defines the computational space. For an input indexable type, the read-only communication operator produces an output indexable type with the same rank and element type as the input indexable type but ensures that the output indexable type may not be written. The read-only communication operator ensures that any attempt to write to the output indexable type will be detected as an error at compile time.Type: GrantFiled: August 30, 2016Date of Patent: April 14, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Yosseff Levanoni, Paul F. Ringseth, Weirong Zhu, Lingli Zhang
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Patent number: 9971710Abstract: Embodiments are directed to optimizing data transfers between heterogeneous memory arenas. In one scenario, a computer system receives an indication that a data chunk is to be transferred from a first memory arena to a third memory arena, and then determines that for the data chunk to be transferred from the first memory arena to the third arena, the data chunk is to be transferred from the first memory arena to a second memory arena, and from the second memory arena to the third memory arena. The computer system divides the data chunk into smaller data portions and copies a first data portion from the first memory arena to the second memory arena. The computer system then copies the first data portion from the second memory arena to the third memory arena and copies a second data portion from the first memory arena to the second memory arena in parallel.Type: GrantFiled: February 7, 2013Date of Patent: May 15, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Amit Kumar Agarwal, Yosseff Levanoni, Weirong Zhu
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Publication number: 20160371061Abstract: A high level programming language provides a read-only communication operator that prevents a computational space from being written. An indexable type with a rank and element type defines the computational space. For an input indexable type, the read-only communication operator produces an output indexable type with the same rank and element type as the input indexable type but ensures that the output indexable type may not be written. The read-only communication operator ensures that any attempt to write to the output indexable type will be detected as an error at compile time.Type: ApplicationFiled: August 30, 2016Publication date: December 22, 2016Applicant: Microsoft Technology Licensing, LLCInventors: Yosseff Levanoni, Paul F. Ringseth, Weirong Zhu, Lingli Zhang
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Patent number: 9430204Abstract: A high level programming language provides a read-only communication operator that prevents a computational space from being written. An indexable type with a rank and element type defines the computational space. For an input indexable type, the read-only communication operator produces an output indexable type with the same rank and element type as the input indexable type but ensures that the output indexable type may not be written. The read-only communication operator ensures that any attempt to write to the output indexable type will be detected as an error at compile time.Type: GrantFiled: November 19, 2010Date of Patent: August 30, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Yosseff Levanoni, Paul F. Ringseth, Weirong Zhu, Lingli Zhang
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Patent number: 9411634Abstract: A software transactional memory system implements a lightweight key-based action framework. The framework includes a set of unified application programming interfaces (APIs) exposed by an STM library that allow clients to implement actions that can be registered, queried, and updated using specific keys by transactions or transaction nests in STM code. Each action includes a key, state information, and a set of one or more callbacks that can be hooked to the validation, commit, abort, and/or re-execution phases of transaction execution. The actions extend the built-in concurrency controls of the STM system with customized control logics, support transaction nesting semantics, and enable integration with garbage collection systems.Type: GrantFiled: June 21, 2010Date of Patent: August 9, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Lingli Zhang, Yosseff Levanoni, David L. Detlefs, Sukhdeep S. Sodhi, Weirong Zhu
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Patent number: 9239803Abstract: A software transactional memory system is provided that creates an array of transactional locks for each array object that is accessed by transactions. The system divides the array object into non-overlapping portions and associates each portion with a different transactional lock. The system acquires transactional locks for transactions that access corresponding portions of the array object. By doing so, different portions of the array object can be accessed by different transactions concurrently. The system may use a shared shadow or undo copy for accesses to the array object.Type: GrantFiled: August 10, 2015Date of Patent: January 19, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Weirong Zhu, David L. Detlefs, Yosseff Levanoni, Lingli Zhang
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Publication number: 20160013966Abstract: Various embodiments enable a group of devices to be logically grouped together in what is referred to as a “device circle.” The devices in a device circle can be bound through static and dynamic bindings. In at least some embodiments, the device circle serves as a single abstract entity that does not necessarily expose its individual constituent devices. As such, communication and other functionality can take place with the device circle in a manner that does not divulge the identities, capabilities, or roles of the individual devices that make up the device circle.Type: ApplicationFiled: July 11, 2014Publication date: January 14, 2016Inventors: Shankar Vaidyanathan, Todd L. Paul, Yosseff Levanoni, Arvind Sethuraman, Weirong Zhu, Lingli Zhang
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Publication number: 20150347323Abstract: A software transactional memory system is provided that creates an array of transactional locks for each array object that is accessed by transactions. The system divides the array object into non-overlapping portions and associates each portion with a different transactional lock. The system acquires transactional locks for transactions that access corresponding portions of the array object. By doing so, different portions of the array object can be accessed by different transactions concurrently. The system may use a shared shadow or undo copy for accesses to the array object.Type: ApplicationFiled: August 10, 2015Publication date: December 3, 2015Inventors: Weirong Zhu, David L. Detlefs, Yosseff Levanoni, Lingli Zhang
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Patent number: 9104628Abstract: A software transactional memory system is provided that creates an array of transactional locks for each array object that is accessed by transactions. The system divides the array object into non-overlapping portions and associates each portion with a different transactional lock. The system acquires transactional locks for transactions that access corresponding portions of the array object. By doing so, different portions of the array object can be accessed by different transactions concurrently. The system may use a shared shadow or undo copy for accesses to the array object.Type: GrantFiled: January 10, 2015Date of Patent: August 11, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Weirong Zhu, David L. Detlefs, Yosseff Levanoni, Lingli Zhang
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Publication number: 20150186165Abstract: The present invention extends to methods, systems, and computer program products for emulating pointers. Pointers can be emulated by replacing the pointers with a variable offset pair and replacing each dereference site with a switch on the tag and a switch body that executes the emulated pointer access on the corresponding variable the pointer points to. Data flow optimizations can be used to reduce the number of switches and/or reduce the number of cases which need be considered at each emulated pointer access sites.Type: ApplicationFiled: March 17, 2015Publication date: July 2, 2015Inventors: Yosseff Levanoni, Weirong Zhu, Lingli Zhang, John Lee Rapp, Andrew L. Bliss
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Publication number: 20150127915Abstract: A software transactional memory system is provided that creates an array of transactional locks for each array object that is accessed by transactions. The system divides the array object into non-overlapping portions and associates each portion with a different transactional lock. The system acquires transactional locks for transactions that access corresponding portions of the array object. By doing so, different portions of the array object can be accessed by different transactions concurrently. The system may use a shared shadow or undo copy for accesses to the array object.Type: ApplicationFiled: January 10, 2015Publication date: May 7, 2015Inventors: Weirong Zhu, David L. Detlefs, Yosseff Levanoni, Lingli Zhang
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Patent number: 8997066Abstract: The present invention extends to methods, systems, and computer program products for emulating pointers. Pointers can be emulated by replacing the pointers with a <variable#, offset> pair and replacing each dereference site with a switch on the tag and a switch body that executes the emulated pointer access on the corresponding variable the pointer points to. Data flow optimizations can be used to reduce the number of switches and/or reduce the number of cases which need be considered at each emulated pointer access sites.Type: GrantFiled: December 27, 2010Date of Patent: March 31, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Yosseff Levanoni, Weirong Zhu, Lingli Zhang, John Lee Rapp, Andrew L. Bliss
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Patent number: 8990515Abstract: The present invention extends to methods, systems, and computer program products for aliasing buffers. Embodiment of the inventions supporting buffer aliasing through introduction of a level of indirection between a source program's buffer accesses and the target executable physical buffers, and binding the logical buffer accesses to actual physical buffer accesses at runtime. A variety of techniques for can be used supporting runtime aliasing of buffers, in a system which otherwise disallows such runtime aliasing between separately defined buffers in the target executable code. Binding of logical buffer accesses in the source program to the actual physical buffers defined in the target executable code is delayed until runtime.Type: GrantFiled: June 14, 2011Date of Patent: March 24, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Amit Kumar Agarwal, Weirong Zhu, Yosseff Levanoni
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Patent number: 8954995Abstract: A software transactional memory system is provided that creates an array of transactional locks for each array object that is accessed by transactions. The system divides the array object into non-overlapping portions and associates each portion with a different transactional lock. The system acquires transactional locks for transactions that access corresponding portions of the array object. By doing so, different portions of the array object can be accessed by different transactions concurrently. The system may use a shared shadow or undo copy for accesses to the array object.Type: GrantFiled: October 1, 2008Date of Patent: February 10, 2015Assignee: Microsoft CorporationInventors: Weirong Zhu, David L. Detlefs, Yosseff Levanoni, Lingli Zhang
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Patent number: 8839214Abstract: A high level programming language provides an extensible set of transformations for use on indexable types in a data parallel processing environment. A compiler for the language implements each transformation as a map from indexable types to allow each transformation to be applied to other transformations. At compile time, the compiler identifies sequences of the transformations on each indexable type in data parallel source code and generates data parallel executable code to implement the sequences as a combined operation at runtime using the transformation maps. The compiler also incorporates optimizations that are based on the sequences of transformations into the data parallel executable code.Type: GrantFiled: June 30, 2010Date of Patent: September 16, 2014Assignee: Microsoft CorporationInventors: Paul F. Ringseth, Weirong Zhu, Rick Molloy, Charles D. Callahan, II, Yosseff Levanoni, Lingli Zhang
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Publication number: 20140223131Abstract: Embodiments are directed to optimizing data transfers between heterogeneous memory arenas. In one scenario, a computer system receives an indication that a data chunk is to be transferred from a first memory arena to a third memory arena, and then determines that for the data chunk to be transferred from the first memory arena to the third arena, the data chunk is to be transferred from the first memory arena to a second memory arena, and from the second memory arena to the third memory arena. The computer system divides the data chunk into smaller data portions and copies a first data portion from the first memory arena to the second memory arena. The computer system then copies the first data portion from the second memory arena to the third memory arena and copies a second data portion from the first memory arena to the second memory arena in parallel.Type: ApplicationFiled: February 7, 2013Publication date: August 7, 2014Applicant: MICROSOFT CORPORATIONInventors: Amit Kumar Agarwal, Yosseff Levanoni, Weirong Zhu
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Patent number: 8756590Abstract: A compile environment is provided in a computer system that allows programmers to program both CPUs and data parallel devices (e.g., GPUs) using a high level general purpose programming language that has data parallel (DP) extensions. A compilation process translates modular DP code written in the general purpose language into DP device source code in a high level DP device programming language using a set of binding descriptors for the DP device source code. A binder generates a single, self-contained DP device source code unit from the set of binding descriptors. A DP device compiler generates a DP device executable for execution on one or more data parallel devices from the DP device source code unit.Type: GrantFiled: June 22, 2010Date of Patent: June 17, 2014Assignee: Microsoft CorporationInventors: Weirong Zhu, Lingli Zhang, Sukhdeep S. Sodhi, Yosseff Levanoni
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Patent number: 8719515Abstract: A software transactional memory (STM) system allows the composition of traditional lock based synchronization with transactions in STM code. The STM system acquires each traditional lock the first time that a corresponding traditional lock acquire is encountered inside a transaction and defers all traditional lock releases until a top level transaction in a transaction nest commits or aborts. The STM system maintains state information associated with traditional lock operations in transactions and uses the state information to eliminate deferred traditional lock operations that are redundant. The STM system integrates with systems that implement garbage collection.Type: GrantFiled: June 21, 2010Date of Patent: May 6, 2014Assignee: Microsoft CorporationInventors: Sukhdeep S. Sodhi, Yosseff Levanoni, David L. Detlefs, Lingli Zhang, Weirong Zhu, Dana Groff, Michael M. Magruder, Charles David Callahan, II