Patents by Inventor Weirong Zhu
Weirong Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8713039Abstract: A high level programming language provides a co-map communication operator that maps an input indexable type to an output indexable type according to a function. The function maps an index space corresponding to the output indexable type to an index space corresponding to the input indexable type. By doing so, the co-map communication operator lifts a function on an index space to a function on an indexable type to allow composability with other communication operators.Type: GrantFiled: December 23, 2010Date of Patent: April 29, 2014Assignee: Microsoft CorporationInventors: Paul F. Ringseth, Yosseff Levanoni, Lingli Zhang, Weirong Zhu, Donald J. McCrady
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Patent number: 8677322Abstract: The present invention extends to methods, systems, and computer program products for debugging in a multiple address space environment. Embodiments of the invention include techniques for recording debug information used for translating between an abstract unified address space and multiple address spaces at a target system (e.g., a co-processor, such as, a GPU or other accelerator). A table is stored in the recorded debug information. The table includes one or more entries mapping compiler assigned IDs to address spaces. During debugging within a symbolic debugger, the recorded debug information can be used for viewing program data across multiple address spaces in a live debugging session.Type: GrantFiled: June 29, 2011Date of Patent: March 18, 2014Assignee: Microsoft CorporationInventors: Amit Kumar Agarwal, Weirong Zhu, Yosseff Levanoni, Yongkang Zhu
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Patent number: 8627292Abstract: A software transactional memory system is provided with overflow handling. The system includes a global version counter with an epoch number and a version number. The system accesses the global version counter prior to and subsequent to memory accesses of transactions to validate read accesses of the transaction. The system includes mechanisms to detect global version number overflow and may allow some or all transactions to execute to completion subsequent to the global version number overflowing. The system also provides publication, privatization, and granular safety properties.Type: GrantFiled: February 13, 2009Date of Patent: January 7, 2014Assignee: Microsoft CorporationInventors: Yosseff Levanoni, David L. Detlefs, Weirong Zhu, Timothy L. Harris, Michael M. Magruder, Matthew B. Tolton
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Patent number: 8589867Abstract: Described herein are techniques for generating invocation stubs for a data parallel programming model so that a data parallel program written in a statically-compiled high-level programming language may be more declarative, reusable, and portable than traditional approaches. With some of the described techniques, invocation stubs are generated by a compiler and those stubs bridge a logical arrangement of data parallel computations to the actual physical arrangement of a target data parallel hardware for that data parallel computation.Type: GrantFiled: June 18, 2010Date of Patent: November 19, 2013Assignee: Microsoft CorporationInventors: Lingli Zhang, Weirong Zhu, Yosseff Levanoni, Paul F. Ringseth, Charles David Callahan, II
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Patent number: 8539458Abstract: The present invention extends to methods, systems, and computer program products for changing addressing mode during code generation. Generally, embodiments of the invention use a compiler transformation to transform lower level code from one address alignment to another address alignment. The transformation can be based upon assumptions of a source programming language. Based on the assumptions, the transformation can eliminate arithmetic operations that compensate for different addressing alignment, resulting in more efficient code. Some particular embodiments use a compiler transformation to transform an Intermediate Representation (“IR”) from one-byte addressing alignment into multi-byte (e.g., four-byte) addressing alignment.Type: GrantFiled: June 10, 2011Date of Patent: September 17, 2013Assignee: Microsoft CorporationInventors: Weirong Zhu, Yosseff Levanoni
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Patent number: 8533698Abstract: The present invention extends to methods, systems, and computer program products for optimizing execution of kernels. Embodiments of the invention include an optimization framework for optimizing runtime execution of kernels. During compilation, information about the execution properties of a kernel are identified and stored alongside the executable code for the kernel. At runtime, calling contexts access the information. The calling contexts interpret the information and optimize kernel execution based on the interpretation.Type: GrantFiled: June 13, 2011Date of Patent: September 10, 2013Assignee: Microsoft CorporationInventors: Weirong Zhu, Amit Kumar Agarwal, Lingli Zhang, Yosseff Levanoni
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Patent number: 8510724Abstract: The present invention extends to methods, systems, and computer program products for reconstructing program control flow. Embodiments include implementing or morphing a control flow graph (“CFG”) into an arbitrary loop structure to reconstruct (preserve) control flow from original source code. Loop structures can be optimized and can adhere to target platform constraints. In some embodiments, C++ source code (a first higher level format) is translated into a CFG (a lower level format). The CFG is then translated into High Level Shader Language (“HLSL”) source code (a second different higher level format) for subsequent compilation into SLSL bytecode (that can then be executed at a Graphical Processing Unit (“GPU”)). The control flow from the C++ source code is preserved in the HLSL source code.Type: GrantFiled: December 17, 2010Date of Patent: August 13, 2013Assignee: Microsoft CorporationInventors: Yosseff Levanoni, Weirong Zhu, Lingli Zhang, John Lee Rapp, Andrew L. Bliss
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Patent number: 8468507Abstract: The present invention extends to methods, systems, and computer program products for binding executable code at runtime. Embodiments of the invention include late binding of specified aspects of code to improve execution performance. A runtime dynamically binds lower level code based on runtime information to optimize execution of a higher level algorithm. Aspects of a higher level algorithm having a requisite (e.g., higher) impact on execution performance can be targeted for late binding. Improved performance can be achieved with minimal runtime costs using late binding for aspects having the requisite execution performance impact.Type: GrantFiled: June 10, 2011Date of Patent: June 18, 2013Assignee: Microsoft CorporationInventors: Amit Kumar Agarwal, Weirong Zhu, Yosseff Levanoni
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Patent number: 8402450Abstract: A high level programming language provides a map transformation that takes a data parallel algorithm and a set of one or more input indexable types as arguments. The map transformation applies the data parallel algorithm to the set of input indexable types to generate an output indexable type, and returns the output indexable type. The map transformation may be used to fuse one or more data parallel algorithms with another data parallel algorithm.Type: GrantFiled: November 17, 2010Date of Patent: March 19, 2013Assignee: Microsoft CorporationInventors: Paul F. Ringseth, Yosseff Levanoni, Weirong Zhu
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Publication number: 20130007712Abstract: The present invention extends to methods, systems, and computer program products for debugging in a multiple address space environment. Embodiments of the invention include techniques for recording debug information used for translating between an abstract unified address space and multiple address spaces at a target system (e.g., a co-processor, such as, a GPU or other accelerator). A table is stored in the recorded debug information. The table includes one or more entries mapping compiler assigned IDs to address spaces. During debugging within a symbolic debugger, the recorded debug information can be used for viewing program data across multiple address spaces in a live debugging session.Type: ApplicationFiled: June 29, 2011Publication date: January 3, 2013Applicant: Microsoft CorporationInventors: Amit Kumar Agarwal, Weirong Zhu, Yosseff Levanoni, Yongkang Zhu
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Publication number: 20120324430Abstract: The present invention extends to methods, systems, and computer program products for aliasing buffers. Embodiment of the inventions supporting buffer aliasing through introduction of a level of indirection between a source program's buffer accesses and the target executable physical buffers, and binding the logical buffer accesses to actual physical buffer accesses at runtime. A variety of techniques for can be used supporting runtime aliasing of buffers, in a system which otherwise disallows such runtime aliasing between separately defined buffers in the target executable code. Binding of logical buffer accesses in the source program to the actual physical buffers defined in the target executable code is delayed until runtime.Type: ApplicationFiled: June 14, 2011Publication date: December 20, 2012Applicant: Microsoft CorporationInventors: Amit Kumar Agarwal, Weirong Zhu, Yosseff Levanoni
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Publication number: 20120317558Abstract: The present invention extends to methods, systems, and computer program products for binding executable code at runtime. Embodiments of the invention include late binding of specified aspects of code to improve execution performance. A runtime dynamically binds lower level code based on runtime information to optimize execution of a higher level algorithm. Aspects of a higher level algorithm having a requisite (e.g., higher) impact on execution performance can be targeted for late binding. Improved performance can be achieved with minimal runtime costs using late binding for aspects having the requisite execution performance impact.Type: ApplicationFiled: June 10, 2011Publication date: December 13, 2012Applicant: Microsoft CorporationInventors: Amit Kumar Agarwal, Weirong Zhu, Yosseff Levanoni
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Publication number: 20120317394Abstract: The present invention extends to methods, systems, and computer program products for changing addressing mode during code generation. Generally, embodiments of the invention use a compiler transformation to transform lower level code from one address alignment to another address alignment. The transformation can be based upon assumptions of a source programming language. Based on the assumptions, the transformation can eliminate arithmetic operations that compensate for different addressing alignment, resulting in more efficient code. Some particular embodiments use a compiler transformation to transform an Intermediate Representation (“IR”) from one-byte addressing alignment into multi-byte (e.g., four-byte) addressing alignment.Type: ApplicationFiled: June 10, 2011Publication date: December 13, 2012Applicant: Microsoft CorporationInventors: Weirong Zhu, Yosseff Levanoni
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Publication number: 20120317556Abstract: The present invention extends to methods, systems, and computer program products for optimizing execution of kernels. Embodiments of the invention include an optimization framework for optimizing runtime execution of kernels. During compilation, information about the execution properties of a kernel are identified and stored alongside the executable code for the kernel. At runtime, calling contexts access the information. The calling contexts interpret the information and optimize kernel execution based on the interpretation.Type: ApplicationFiled: June 13, 2011Publication date: December 13, 2012Applicant: Microsoft CorporationInventors: Weirong Zhu, Amit Kumar Agarwal, Lingli Zhang, Yosseff Levanoni
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Patent number: 8266604Abstract: Transactional memory compatibility type attributes are associated with intermediate language code to specify, for example, that intermediate language code must be run within a transaction, or must not be run within a transaction, or may be run within a transaction. Attributes are automatically produced while generating intermediate language code from annotated source code. Default rules also generate attributes. Tools use attributes to statically or dynamically check for incompatibility between intermediate language code and a transactional memory implementation.Type: GrantFiled: January 26, 2009Date of Patent: September 11, 2012Assignee: Microsoft CorporationInventors: Dana Groff, Yosseff Levanoni, Stephen Toub, Michael McKenzie Magruder, Weirong Zhu, Timothy Lawrence Harris, Christopher William Dern, John Joseph Duffy, David Detlefs, Martin Abadi, Sukhdeep Singh Sodhi, Lingli Zhang, Alexander Dadiomov, Vinod Grover
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Publication number: 20120166444Abstract: A high level programming language provides a co-map communication operator that maps an input indexable type to an output indexable type according to a function. The function maps an index space corresponding to the output indexable type to an index space corresponding to the input indexable type. By doing so, the co-map communication operator lifts a function on an index space to a function on an indexable type to allow composability with other communication operators.Type: ApplicationFiled: December 23, 2010Publication date: June 28, 2012Applicant: MICROSOFT CORPORATIONInventors: Paul F. Ringseth, Yosseff Levanoni, Lingli Zhang, Weirong Zhu, Donald J. McCrady
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Publication number: 20120167062Abstract: The present invention extends to methods, systems, and computer program products for emulating pointers. Pointers can be emulated by replacing the pointers with a <variable#, offset> pair and replacing each dereference site with a switch on the tag and a switch body that executes the emulated pointer access on the corresponding variable the pointer points to. Data flow optimizations can be used to reduce the number of switches and/or reduce the number of cases which need be considered at each emulated pointer access sites.Type: ApplicationFiled: December 27, 2010Publication date: June 28, 2012Applicant: Microsoft CorporationInventors: Yosseff Levanoni, Weirong Zhu, Lingli Zhang, John Lee Rapp, Andrew L. Bliss
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Publication number: 20120159458Abstract: The present invention extends to methods, systems, and computer program products for reconstructing program control flow. Embodiments include implementing or morphing a control flow graph (“CFG”) into an arbitrary loop structure to reconstruct (preserve) control flow from original source code. Loop structures can be optimized and can adhere to target platform constraints. In some embodiments, C++ source code (a first higher level format) is translated into a CFG (a lower level format). The CFG is then translated into HLSL source code (a second different higher level format) for subsequent compilation into SLSL bytecode (that can then be executed at a Graphical Processing Unit (“GPU”)). The control flow from the C++ source code is preserved in the HLSL source code.Type: ApplicationFiled: December 17, 2010Publication date: June 21, 2012Applicant: Microsoft CorporationInventors: Yosseff Levanoni, Weirong Zhu, Lingli Zhang, John Lee Rapp, Andrew L. Bliss
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Publication number: 20120131552Abstract: A high level programming language provides a read-only communication operator that prevents a computational space from being written. An indexable type with a rank and element type defines the computational space. For an input indexable type, the read-only communication operator produces an output indexable type with the same rank and element type as the input indexable type but ensures that the output indexable type may not be written. The read-only communication operator ensures that any attempt to write to the output indexable type will be detected as an error at compile time.Type: ApplicationFiled: November 19, 2010Publication date: May 24, 2012Applicant: MICROSOFT CORPORATIONInventors: Yosseff Levanoni, Paul F. Ringseth, Weirong Zhu, Lingli Zhang
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Publication number: 20120124564Abstract: A high level programming language provides a map transformation that takes a data parallel algorithm and a set of one or more input indexable types as arguments. The map transformation applies the data parallel algorithm to the set of input indexable types to generate an output indexable type, and returns the output indexable type. The map transformation may be used to fuse one or more data parallel algorithms with another data parallel algorithm.Type: ApplicationFiled: November 17, 2010Publication date: May 17, 2012Applicant: MICROSOFT CORPORATIONInventors: Paul F. Ringseth, Yosseff Levanoni, Weirong Zhu