Abstract: A computer readable storage medium is provided. When contents of the computer readable storage medium are executed by a processor, multi-photon imaging may be performed on a histopathological section containing tumor environment information, and pathological partitioning of a tumor microenvironment may be further performed through image processing. A value of each collagen feature parameters, such as a morphological feature parameter, an energy feature parameter and a texture feature parameter, may be extracted from a tumor tissue region, an invasive margin (IM) region and a normal tissue (N) region. An inter-region difference and a variation may be calculated according to feature parameters of regions. A collagen feature scoring model may be established. A collagen feature score may be calculated with the collagen feature parameters input to the model.

Abstract: Disclosed are an ultrafast electric pulse generation and detection device and a use method thereof. The device includes a laser and an electric pulse generator. The electric pulse generator includes: a photoelectric material layer including an optically controlled switching region for responding to excitation light generated by the laser; an insulating layer formed on the photoelectric material layer, wherein a switch structure exists at a position of the insulating layer corresponding to the optically controlled switching region, so that the optically controlled switching region is partially exposed or completely exposed; transmission lines are formed on the insulating layer.

Abstract: Disclosed are a low-loss coplanar waveguide bonding structure and a manufacturing method thereof, relating to the technical field of semiconductor. The low-loss coplanar waveguide bonding structure includes: a first coplanar waveguide on a first substrate, a second coplanar waveguide on a second substrate and having a same structure as the first coplanar waveguide, and a plurality of two-dimensional heterostructures connecting conductors of the first coplanar waveguide and the second coplanar waveguide in a one-to-one correspondence, where the two-dimensional heterostructures includes: a two-dimensional conductive material layer for signal transmission and a two-dimensional dielectric material layer under the two-dimensional conductive material layer.

Abstract: Disclosed are a memory array, a memory, a preparing method and a writing method. Some embodiments relate to a memory array for a magnetoresistive random access memory and a manufacturing method thereof. The memory array includes: a plurality of memory cells arranged in an array and a conductor layer; each of the memory cells includes: a write transistor, a first end of which is coupled to top electrode wiring; a magnetic tunnel junction MTJ, one end of which close to a reference layer is coupled to a second end of the write transistor; a side surface of the conductor layer is coupled to end faces of one end of all of the magnetic tunnel junctions MTJs close to a free layer.

Abstract: The present disclosure provides a multi-bit memory cell, an analog-to-digital converter, a device and a method. The multi-bit memory cell comprises: a spin-orbit coupling layer and a plurality of magnetic tunnel junctions disposed on the spin-orbit coupling layer, the plurality of magnetic tunnel junctions comprising a plurality of first magnetic tunnel junctions; the plurality of first magnetic tunnel junctions are sequentially arranged along a length direction of the spin-orbit coupling layer, and critical currents of reversals of the magnetizations of free layers of the plurality of first magnetic tunnel junctions are progressively increased or decreased in sequence along the length direction. The present disclosure provides a multi-bit memory unit with simple manufacturing process and structure.

Abstract: The present disclosure provides a multi-bit memory cell, an analog-to-digital converter, a device and a method. The multi-bit memory cell comprises: a spin-orbit coupling layer and a plurality of magnetic tunnel junctions disposed on the spin-orbit coupling layer, the plurality of magnetic tunnel junctions comprising a plurality of first magnetic tunnel junctions; the plurality of first magnetic tunnel junctions are sequentially arranged along a length direction of the spin-orbit coupling layer, and critical currents of reversals of the magnetizations of free layers of the plurality of first magnetic tunnel junctions are progressively increased or decreased in sequence along the length direction. The present disclosure provides a multi-bit memory unit with simple manufacturing process and structure.

Abstract: The present disclosure provides a magnetic random-access memory cell, a memory and a device. The magnetic random-access memory cell comprises: a spin-orbit coupling layer and a first magnetic tunnel junction and a second magnetic tunnel junction disposed on the spin-orbit coupling layer, the first magnetic tunnel junction and the second magnetic tunnel junction having at least two symmetrical axes with different lengths; an angle between an easy magnetization symmetrical axis direction of a free layer of the first magnetic tunnel junction and a length direction of the spin-orbit coupling layer is a preset first angle, and an angle between an easy magnetization symmetrical axis direction of a free layer of the second magnetic tunnel junction and the length direction of the spin-orbit coupling layer is a preset second angle; neither of the first angle and the second angle is zero degree, 90 degrees or 180 degrees.

Abstract: The present disclosure provides a magnetic random-access memory, comprising: an antiferromagnetic layer; a magnetic tunnel junction disposed on the antiferromagnetic layer and comprising a ferromagnetic layer disposed corresponding to the antiferromagnetic layer; wherein the ferromagnetic layer of the magnetic tunnel junction has in-plane magnetic anisotropy, and an exchange bias field is formed between the antiferromagnetic layer and the ferromagnetic layer by an annealing process. A direction of the exchange bias field is changed by a spin orbit torque, thereby changing a direction of a magnetic moment of the ferromagnetic layer and realizing data writing. The present disclosure can improve a thermal stability of the i-MTJ and reduce a lateral dimension of the i-MTJ, thereby improving a storage density of the magnetic memory.

Abstract: A highly reliable STT-MRAM structure and an implementation method thereof are provided. The STT-MRAM structure includes: a memory block array, including a plurality of memory blocks; on-chip in-situ temperature sensors, for detecting an instantaneous temperature of each memory block; and a controller, which outputs a reading or writing operation signal based on the instantaneous temperature of each memory block detected by the on-chip in-situ temperature sensors, so as to modulate respective voltages and/or frequencies of reading and writing operations of each memory block. When the instantaneous temperature is too high, the voltages and/or frequencies of the reading and writing operations would be decreased, to the contrary when the instantaneous temperature is too low, the voltages and/or frequencies of the reading and writing operations would be increased, which expands a reliable working temperature range and lengthens a lifetime of the STT-MRAM structure.

Abstract: A computing in-memory system and computing in-memory method based on a skyrmion race memory are provided. The system comprises a circuit architecture of SRM-CIM. The circuit architecture of the SRM-CIM comprises a row decoder, a column decoder, a voltage-driven, a storage array, a modified sensor circuit, a counter Bit-counter and a mode controller. The voltage-driven includes two NMOSs, and the two NMOSs are respectively connected with a selector MUX. The modified sensor circuit compares the resistance between a first node to a second node and a third node to a fourth node by using a pre-charge sense amplifier. The storage array is composed of the skyrmion racetrack memories. The computing in-memory architecture is designed by utilizing the skyrmion racetrack memory, so that storage is realized in the memory, and computing operation can be carried out in the memory.

Abstract: A complementary magnetic memory cell includes: a heavy metal film or an antiferromagnetic film, a first magnetic tunnel junction, a second magnetic tunnel junction, a first electrode, a second electrode, a third electrode, a fourth electrode, and a fifth electrode; wherein the first magnetic tunnel junction and the second magnetic tunnel junction are fabricated above the heavy metal film or the antiferromagnetic film; the first electrode, the second electrode and the third electrode are fabricated under the heavy metal film or the antiferromagnetic film; the fourth electrode is fabricated above the first magnetic tunnel junction, and the fifth electrode is fabricated above the second magnetic tunnel junction; to store one bit of data, the first magnetic tunnel junction and the second magnetic tunnel junction are arranged in a pair of complementary resistance states, wherein one magnetic tunnel junction is set to a high resistance state and the other remains unchanged.

Abstract: A computing in-memory system and computing in-memory method based on a skyrmion race memory are provided. The system comprises a circuit architecture of SRM-CIM. The circuit architecture of the SRM-CIM comprises a row decoder, a column decoder, a voltage-driven, a storage array, a modified sensor circuit, a counter Bit-counter and a mode controller. The voltage-driven includes two NMOSs, and the two NMOSs are respectively connected with a selector MUX. The modified sensor circuit compares the resistance between a first node to a second node and a third node to a fourth node by using a pre-charge sense amplifier. The storage array is composed of the skyrmion racetrack memories. The computing in-memory architecture is designed by utilizing the skyrmion racetrack memory, so that storage is realized in the memory, and computing operation can be carried out in the memory.

Abstract: A magnetic tunnel junction reference layer, magnetic tunnel junctions and a magnetic random access memory are provided, wherein the magnetic tunnel junction reference layer includes: an antiferromagnetic structure layer, which comprises a plurality of stacked metal magnetic layer units, wherein each of the metal magnetic layer units comprises a spacer layer and a magnetic layer on a surface of the spacer layer. The present invention forms a synthetic antiferromagnetic structure through multilayer stack of the metal spacer layer and the magnetic layer, so as to increase thermal stability of the magnetic tunnel junction reference layer with perpendicular magnetic anisotropy and reduce design complexity as well as cost of the film layers. The present invention forms a multilayer film structure without oxides, which has strong perpendicular magnetic anisotropy, high thermal stability, simple film layer, and low cost, thereby promoting large-scale use of the magnetic memory.

Abstract: A highly reliable STT-MRAM structure and an implementation method thereof are provided. The STT-MRAM structure includes: a memory block array, including a plurality of memory blocks; on-chip in-situ temperature sensors, for detecting an instantaneous temperature of each memory block; and a controller, which outputs a reading or writing operation signal based on the instantaneous temperature of each memory block detected by the on-chip in-situ temperature sensors, so as to modulate respective voltages and/or frequencies of reading and writing operations of each memory block. When the instantaneous temperature is too high, the voltages and/or frequencies of the reading and writing operations would be decreased, to the contrary when the instantaneous temperature is too low, the voltages and/or frequencies of the reading and writing operations would be increased, which expands a reliable working temperature range and lengthens a lifetime of the STT-MRAM structure.

Abstract: A magnetic memory includes one or more magnetic tunnel junctions, a heavy metal or anti-ferromagnetic strip film, a first bottom electrode and a second bottom electrode. Every magnetic tunnel junction is located on the strip film and represents a memory cell; the first bottom electrode and the second bottom electrode are respectively connected with two ends of the heavy metal or anti-ferromagnetic strip film; every magnetic tunnel junction includes a first ferromagnetic metal, a first oxide, a second ferromagnetic metal, a first synthetic antiferromagnetic layer and an Xth top electrode from bottom to top in sequence, wherein X is a serial number of the memory cell. A data writing method combines spin orbit torque with spin transfer torque to write data, and respectively applies two currents to the magnetic tunnel junction and the heavy metal or anti-ferromagnetic strip film. Only one current is unable to complete data writing.

Abstract: A complementary magnetic memory cell includes: a heavy metal film or an antiferromagnetic film, a first magnetic tunnel junction, a second magnetic tunnel junction, a first electrode, a second electrode, a third electrode, a fourth electrode, and a fifth electrode; wherein the first magnetic tunnel junction and the second magnetic tunnel junction are fabricated above the heavy metal film or the antiferromagnetic film; the first electrode, the second electrode and the third electrode are fabricated under the heavy metal film or the antiferromagnetic film; the fourth electrode is fabricated above the first magnetic tunnel junction, and the fifth electrode is fabricated above the second magnetic tunnel junction; to store one bit of data, the first magnetic tunnel junction and the second magnetic tunnel junction are arranged in a pair of complementary resistance states, wherein one magnetic tunnel junction is set to a high resistance state and the other remains unchanged.

Abstract: A magnetic tunnel junction (MTJ) includes a first iridium layer, a first tungsten layer, a first ferromagnetic layer, a tunneling barrier layer, a second ferromagnetic layer, a second tungsten layer and a second iridium layer in sequence, wherein the two ferromagnetic layers are respectively a reference layer with a fixed magnetization direction and a free layer with a reversible magnetization direction. When the magnetization direction of the reference layer is parallel to the magnetization direction of the free layer, the MTJ is in a low-resistance state to store a binary digit “0”; when the magnetization direction of the reference layer is anti-parallel to the magnetization direction of the free layer, the MTJ is in a high-resistance state to store a binary digit “1”. The present invention can enhance tunneling magnetoresistance effect by using iridium layer, improve read reliability and reduce writing power consumption of the MTJ.

Abstract: A magnetic memory includes one or more magnetic tunnel junctions, a heavy metal or anti-ferromagnetic strip film, a first bottom electrode and a second bottom electrode. Every magnetic tunnel junction is located on the strip film and represents a memory cell; the first bottom electrode and the second bottom electrode are respectively connected with two ends of the heavy metal or anti-ferromagnetic strip film; every magnetic tunnel junction includes a first ferromagnetic metal, a first oxide, a second ferromagnetic metal, a first synthetic antiferromagnetic layer and an Xth top electrode from bottom to top in sequence, wherein X is a serial number of the memory cell. A data writing method combines spin orbit torque with spin transfer torque to write data, and respectively applies two currents to the magnetic tunnel junction and the heavy metal or anti-ferromagnetic strip film. Only one current is unable to complete data writing.

Abstract: A high-density magnetic memory device includes: a heavy metal strip or an antiferromagnet strip with a thickness of 0-20 nm, and a plurality of magnetic tunnel junctions manufactured thereon, wherein each of the magnetic tunnel junctions represents a memory bit, which from bottom to top comprises a first ferromagnetic metal with a thickness of 0-3 nm, an oxide with a thickness of 0-2 nm, a second ferromagnetic metal with a thickness of 0-3 nm, a synthetic antiferromagnetic layer with a thickness of 10-20 nm and a No. X top electrode with a thickness of 10-200 nm, wherein an X value is a serial number of the memory bit; two ends of the heavy metal strip or the antiferromagnet strip are respectively plated with a first bottom electrode and a second bottom electrode. The write operation for the memory device of the present invention is accomplished by applying unidirectional write currents.

Abstract: A high-density magnetic memory device includes: a heavy metal strip or an antiferromagnet strip with a thickness of 0-20 nm, and a plurality of magnetic tunnel junctions manufactured thereon, wherein each of the magnetic tunnel junctions represents a memory bit, which from bottom to top comprises a first ferromagnetic metal with a thickness of 0-3 nm, an oxide with a thickness of 0-2 nm, a second ferromagnetic metal with a thickness of 0-3 nm, a synthetic antiferromagnetic layer with a thickness of 10-20 nm and a No. X top electrode with a thickness of 10-200 nm, wherein an X value is a serial number of the memory bit; two ends of the heavy metal strip or the antiferromagnet strip are respectively plated with a first bottom electrode and a second bottom electrode. The write operation for the memory device of the present invention is accomplished by applying unidirectional write currents.