Patents by Inventor Weisheng Zhao

Weisheng Zhao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10910029
    Abstract: A complementary magnetic memory cell includes: a heavy metal film or an antiferromagnetic film, a first magnetic tunnel junction, a second magnetic tunnel junction, a first electrode, a second electrode, a third electrode, a fourth electrode, and a fifth electrode; wherein the first magnetic tunnel junction and the second magnetic tunnel junction are fabricated above the heavy metal film or the antiferromagnetic film; the first electrode, the second electrode and the third electrode are fabricated under the heavy metal film or the antiferromagnetic film; the fourth electrode is fabricated above the first magnetic tunnel junction, and the fifth electrode is fabricated above the second magnetic tunnel junction; to store one bit of data, the first magnetic tunnel junction and the second magnetic tunnel junction are arranged in a pair of complementary resistance states, wherein one magnetic tunnel junction is set to a high resistance state and the other remains unchanged.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: February 2, 2021
    Assignee: BEIHANG UNIVERSITY
    Inventors: Weisheng Zhao, Zhaohao Wang, Erya Deng
  • Publication number: 20210019596
    Abstract: A computing in-memory system and computing in-memory method based on a skyrmion race memory are provided. The system comprises a circuit architecture of SRM-CIM. The circuit architecture of the SRM-CIM comprises a row decoder, a column decoder, a voltage-driven, a storage array, a modified sensor circuit, a counter Bit-counter and a mode controller. The voltage-driven includes two NMOSs, and the two NMOSs are respectively connected with a selector MUX. The modified sensor circuit compares the resistance between a first node to a second node and a third node to a fourth node by using a pre-charge sense amplifier. The storage array is composed of the skyrmion racetrack memories. The computing in-memory architecture is designed by utilizing the skyrmion racetrack memory, so that storage is realized in the memory, and computing operation can be carried out in the memory.
    Type: Application
    Filed: April 25, 2019
    Publication date: January 21, 2021
    Applicants: HEFEI INNOVATION RESEARCH INSTITUTE, BEIHANG UNIVERSITY, BEIHANG UNIVERSITY
    Inventors: Peng OUYANG, Yu PAN, Youguang ZHANG, Weisheng ZHAO
  • Publication number: 20200357983
    Abstract: A magnetic tunnel junction reference layer, magnetic tunnel junctions and a magnetic random access memory are provided, wherein the magnetic tunnel junction reference layer includes: an antiferromagnetic structure layer, which comprises a plurality of stacked metal magnetic layer units, wherein each of the metal magnetic layer units comprises a spacer layer and a magnetic layer on a surface of the spacer layer. The present invention forms a synthetic antiferromagnetic structure through multilayer stack of the metal spacer layer and the magnetic layer, so as to increase thermal stability of the magnetic tunnel junction reference layer with perpendicular magnetic anisotropy and reduce design complexity as well as cost of the film layers. The present invention forms a multilayer film structure without oxides, which has strong perpendicular magnetic anisotropy, high thermal stability, simple film layer, and low cost, thereby promoting large-scale use of the magnetic memory.
    Type: Application
    Filed: July 23, 2020
    Publication date: November 12, 2020
    Inventors: Weisheng Zhao, Houyi Cheng, Kaihua Cao, Gefei Wang
  • Publication number: 20200342927
    Abstract: A highly reliable STT-MRAM structure and an implementation method thereof are provided. The STT-MRAM structure includes: a memory block array, including a plurality of memory blocks; on-chip in-situ temperature sensors, for detecting an instantaneous temperature of each memory block; and a controller, which outputs a reading or writing operation signal based on the instantaneous temperature of each memory block detected by the on-chip in-situ temperature sensors, so as to modulate respective voltages and/or frequencies of reading and writing operations of each memory block. When the instantaneous temperature is too high, the voltages and/or frequencies of the reading and writing operations would be decreased, to the contrary when the instantaneous temperature is too low, the voltages and/or frequencies of the reading and writing operations would be increased, which expands a reliable working temperature range and lengthens a lifetime of the STT-MRAM structure.
    Type: Application
    Filed: July 14, 2020
    Publication date: October 29, 2020
    Inventors: Weisheng Zhao, Kaihua Cao, Erya Deng, Wenlong Cai, Shaohua Yan
  • Patent number: 10388344
    Abstract: A magnetic memory includes one or more magnetic tunnel junctions, a heavy metal or anti-ferromagnetic strip film, a first bottom electrode and a second bottom electrode. Every magnetic tunnel junction is located on the strip film and represents a memory cell; the first bottom electrode and the second bottom electrode are respectively connected with two ends of the heavy metal or anti-ferromagnetic strip film; every magnetic tunnel junction includes a first ferromagnetic metal, a first oxide, a second ferromagnetic metal, a first synthetic antiferromagnetic layer and an Xth top electrode from bottom to top in sequence, wherein X is a serial number of the memory cell. A data writing method combines spin orbit torque with spin transfer torque to write data, and respectively applies two currents to the magnetic tunnel junction and the heavy metal or anti-ferromagnetic strip film. Only one current is unable to complete data writing.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: August 20, 2019
    Assignee: BEIHANG UNIVERSITY
    Inventors: Weisheng Zhao, Zhaohao Wang, Mengxing Wang, Wenlong Cai
  • Publication number: 20190051339
    Abstract: A complementary magnetic memory cell includes: a heavy metal film or an antiferromagnetic film, a first magnetic tunnel junction, a second magnetic tunnel junction, a first electrode, a second electrode, a third electrode, a fourth electrode, and a fifth electrode; wherein the first magnetic tunnel junction and the second magnetic tunnel junction are fabricated above the heavy metal film or the antiferromagnetic film; the first electrode, the second electrode and the third electrode are fabricated under the heavy metal film or the antiferromagnetic film; the fourth electrode is fabricated above the first magnetic tunnel junction, and the fifth electrode is fabricated above the second magnetic tunnel junction; to store one bit of data, the first magnetic tunnel junction and the second magnetic tunnel junction are arranged in a pair of complementary resistance states, wherein one magnetic tunnel junction is set to a high resistance state and the other remains unchanged.
    Type: Application
    Filed: October 16, 2018
    Publication date: February 14, 2019
    Inventors: Weisheng Zhao, Zhaohao Wang, Erya Deng
  • Publication number: 20190035447
    Abstract: A magnetic tunnel junction (MTJ) includes a first iridium layer, a first tungsten layer, a first ferromagnetic layer, a tunneling barrier layer, a second ferromagnetic layer, a second tungsten layer and a second iridium layer in sequence, wherein the two ferromagnetic layers are respectively a reference layer with a fixed magnetization direction and a free layer with a reversible magnetization direction. When the magnetization direction of the reference layer is parallel to the magnetization direction of the free layer, the MTJ is in a low-resistance state to store a binary digit “0”; when the magnetization direction of the reference layer is anti-parallel to the magnetization direction of the free layer, the MTJ is in a high-resistance state to store a binary digit “1”. The present invention can enhance tunneling magnetoresistance effect by using iridium layer, improve read reliability and reduce writing power consumption of the MTJ.
    Type: Application
    Filed: September 28, 2018
    Publication date: January 31, 2019
    Inventors: Weisheng Zhao, Jiaqi Zhou
  • Publication number: 20180277184
    Abstract: A magnetic memory includes one or more magnetic tunnel junctions, a heavy metal or anti-ferromagnetic strip film, a first bottom electrode and a second bottom electrode. Every magnetic tunnel junction is located on the strip film and represents a memory cell; the first bottom electrode and the second bottom electrode are respectively connected with two ends of the heavy metal or anti-ferromagnetic strip film; every magnetic tunnel junction includes a first ferromagnetic metal, a first oxide, a second ferromagnetic metal, a first synthetic antiferromagnetic layer and an Xth top electrode from bottom to top in sequence, wherein X is a serial number of the memory cell. A data writing method combines spin orbit torque with spin transfer torque to write data, and respectively applies two currents to the magnetic tunnel junction and the heavy metal or anti-ferromagnetic strip film. Only one current is unable to complete data writing.
    Type: Application
    Filed: May 25, 2018
    Publication date: September 27, 2018
    Inventors: Weisheng Zhao, Zhaohao Wang, Mengxing Wang, Wenlong Cai
  • Patent number: 10020044
    Abstract: A high-density magnetic memory device includes: a heavy metal strip or an antiferromagnet strip with a thickness of 0-20 nm, and a plurality of magnetic tunnel junctions manufactured thereon, wherein each of the magnetic tunnel junctions represents a memory bit, which from bottom to top comprises a first ferromagnetic metal with a thickness of 0-3 nm, an oxide with a thickness of 0-2 nm, a second ferromagnetic metal with a thickness of 0-3 nm, a synthetic antiferromagnetic layer with a thickness of 10-20 nm and a No. X top electrode with a thickness of 10-200 nm, wherein an X value is a serial number of the memory bit; two ends of the heavy metal strip or the antiferromagnet strip are respectively plated with a first bottom electrode and a second bottom electrode. The write operation for the memory device of the present invention is accomplished by applying unidirectional write currents.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: July 10, 2018
    Assignee: BEIHANG UNIVERSITY
    Inventors: Weisheng Zhao, Zhaohao Wang, Mengxing Wang, Lei Zhang
  • Publication number: 20180061482
    Abstract: A high-density magnetic memory device includes: a heavy metal strip or an antiferromagnet strip with a thickness of 0-20 nm, and a plurality of magnetic tunnel junctions manufactured thereon, wherein each of the magnetic tunnel junctions represents a memory bit, which from bottom to top comprises a first ferromagnetic metal with a thickness of 0-3 nm, an oxide with a thickness of 0-2 nm, a second ferromagnetic metal with a thickness of 0-3 nm, a synthetic antiferromagnetic layer with a thickness of 10-20 nm and a No. X top electrode with a thickness of 10-200 nm, wherein an X value is a serial number of the memory bit; two ends of the heavy metal strip or the antiferromagnet strip are respectively plated with a first bottom electrode and a second bottom electrode. The write operation for the memory device of the present invention is accomplished by applying unidirectional write currents.
    Type: Application
    Filed: October 26, 2017
    Publication date: March 1, 2018
    Inventors: Weisheng Zhao, Zhaohao Wang, Mengxing Wang, Lei Zhang
  • Patent number: 9305607
    Abstract: An architecture and method are provided for reading and writing, in parallel or in series, an electronic memory component based on a two-dimensional matrix of two-terminal binary memory unit cells built into a crossbar architecture. The component includes a logical column-selector located outside the matrix and activating at least one column, one or more cells of which are subjected to read or write processing. Also provided is a component and method with the reading of the status of the cells by differential detection on from two cells of two different rows, either between a storage column and a constant reference column, or between two rows or two storage columns. A component is also provided in which specific selection structure is exclusively dedicated to read operations, and/or in which complementary cells in two complementary columns connected together are encoded in a single atomic operation by means of a single write current.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: April 5, 2016
    Assignees: UNIVERSITE PARIS SUD 11, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Weisheng Zhao, Sumanta Chaudhuri, Claude Chappert, Jacques-Olivier Klein
  • Publication number: 20140016390
    Abstract: An architecture and method are provided for reading and writing, in parallel or in series, an electronic memory component based on a two-dimensional matrix of two-terminal binary memory unit cells built into a crossbar architecture. The component includes a logical column-selector located outside the matrix and activating at least one column, one or more cells of which are subjected to read or write processing. Also provided is a component and method with the reading of the status of the cells by differential detection on from two cells of two different rows, either between a storage column and a constant reference column, or between two rows or two storage columns. A component is also provided in which specific selection structure is exclusively dedicated to read operations, and/or in which complementary cells in two complementary columns connected together are encoded in a single atomic operation by means of a single write current.
    Type: Application
    Filed: March 23, 2012
    Publication date: January 16, 2014
    Inventors: Weisheng Zhao, Sumanta Chaudhuri, Claude Chappert, Jacques-Olivier Klein