Abstract: A high-density magnetic memory device includes: a heavy metal strip or an antiferromagnet strip with a thickness of 0-20 nm, and a plurality of magnetic tunnel junctions manufactured thereon, wherein each of the magnetic tunnel junctions represents a memory bit, which from bottom to top comprises a first ferromagnetic metal with a thickness of 0-3 nm, an oxide with a thickness of 0-2 nm, a second ferromagnetic metal with a thickness of 0-3 nm, a synthetic antiferromagnetic layer with a thickness of 10-20 nm and a No. X top electrode with a thickness of 10-200 nm, wherein an X value is a serial number of the memory bit; two ends of the heavy metal strip or the antiferromagnet strip are respectively plated with a first bottom electrode and a second bottom electrode. The write operation for the memory device of the present invention is accomplished by applying unidirectional write currents.

Abstract: A high-density magnetic memory device includes: a heavy metal strip or an antiferromagnet strip with a thickness of 0-20 nm, and a plurality of magnetic tunnel junctions manufactured thereon, wherein each of the magnetic tunnel junctions represents a memory bit, which from bottom to top comprises a first ferromagnetic metal with a thickness of 0-3 nm, an oxide with a thickness of 0-2 nm, a second ferromagnetic metal with a thickness of 0-3 nm, a synthetic antiferromagnetic layer with a thickness of 10-20 nm and a No. X top electrode with a thickness of 10-200 nm, wherein an X value is a serial number of the memory bit; two ends of the heavy metal strip or the antiferromagnet strip are respectively plated with a first bottom electrode and a second bottom electrode. The write operation for the memory device of the present invention is accomplished by applying unidirectional write currents.

Abstract: An architecture and method are provided for reading and writing, in parallel or in series, an electronic memory component based on a two-dimensional matrix of two-terminal binary memory unit cells built into a crossbar architecture. The component includes a logical column-selector located outside the matrix and activating at least one column, one or more cells of which are subjected to read or write processing. Also provided is a component and method with the reading of the status of the cells by differential detection on from two cells of two different rows, either between a storage column and a constant reference column, or between two rows or two storage columns. A component is also provided in which specific selection structure is exclusively dedicated to read operations, and/or in which complementary cells in two complementary columns connected together are encoded in a single atomic operation by means of a single write current.

Abstract: An architecture and method are provided for reading and writing, in parallel or in series, an electronic memory component based on a two-dimensional matrix of two-terminal binary memory unit cells built into a crossbar architecture. The component includes a logical column-selector located outside the matrix and activating at least one column, one or more cells of which are subjected to read or write processing. Also provided is a component and method with the reading of the status of the cells by differential detection on from two cells of two different rows, either between a storage column and a constant reference column, or between two rows or two storage columns. A component is also provided in which specific selection structure is exclusively dedicated to read operations, and/or in which complementary cells in two complementary columns connected together are encoded in a single atomic operation by means of a single write current.