Patents by Inventor Wei-Yu Chen

Wei-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12386617
    Abstract: An apparatus to facilitate gathering payload from arbitrary registers for send messages in a graphics environment is disclosed. The apparatus includes processing resources comprising execution circuitry to receive a send gather message instruction identifying a number of registers to access for a send message and identifying IDs of a plurality of individual registers corresponding to the number of registers; decode a first phase of the send gather message instruction; based on decoding the first phase, cause a second phase of the send gather message instruction to bypass an instruction decode stage; and dispatch the first phase subsequently followed by dispatch of the second phase to a send pipeline. The apparatus can also perform an immediate move of the IDs of the plurality of individual registers to an architectural register of the execution circuitry and include a pointer to the architectural register in the send gather message instruction.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: August 12, 2025
    Assignee: INTEL CORPORATION
    Inventors: Supratim Pal, Chandra Gurram, Fan-Yin Tzeng, Subramaniam Maiyuran, Guei-Yuan Lueh, Timothy R. Bauer, Vikranth Vemulapalli, Wei-Yu Chen
  • Patent number: 12369173
    Abstract: A method and apparatus are disclosed from the perspective of a first device. In one embodiment, the method includes the first device performs sensing on a data resource pool, and the first device selects/derives at least a first data resource from the data resource pool based on the sensing result of the data resource pool. The method further includes the first device transmits a first control information on a first control resource, wherein the first control information allocates or indicates the first data resource. The method also includes the first device performs a first data transmission on the first data resource to at least one second device.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: July 22, 2025
    Assignee: ASUSTek Computer Inc.
    Inventors: Ming-Che Li, Li-Chih Tseng, Wei-Yu Chen, Li-Te Pan
  • Patent number: 12352932
    Abstract: An optical image capturing system comprising, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. The first lens element with negative refractive power has a concave image-side surface. The second lens element, the third lens element and the fourth lens element have refractive power. The fifth lens element has refractive power. The sixth lens element with refractive power has an image-side surface being concave in a paraxial region and includes at least one convex shape in an off-axial region, wherein the surfaces thereof are aspheric. The seventh lens element with refractive power has an image-side surface being concave in a paraxial region and includes at least one convex shape in an off-axial region, wherein the surfaces thereof are aspheric.
    Type: Grant
    Filed: October 3, 2023
    Date of Patent: July 8, 2025
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Lin-Yao Liao, Dung-Yi Hsieh, Wei-Yu Chen
  • Patent number: 12352930
    Abstract: An imaging optical lens assembly includes nine lens elements which are, in order from an object side to an image side along an optical path: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element, a seventh lens element, an eighth lens element and a ninth lens element. The first lens element has positive refractive power. The eighth lens element with positive refractive power has an image-side surface being convex in a paraxial region thereof. The ninth lens element has an image-side surface being concave in a paraxial region thereof, and the image-side surface of the ninth lens element has at least one convex critical point in an off-axis region thereof.
    Type: Grant
    Filed: February 23, 2024
    Date of Patent: July 8, 2025
    Assignee: LARGAN PRECISION CO., LTD.
    Inventor: Wei-Yu Chen
  • Publication number: 20250218861
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an indentation inwardly positioned in the substrate and comprising a bottom surface and two sidewalls; a catalytic conductive layer positioned on the bottom surface of the indentation. The bottom surface of the indentation and a top surface of the substrate are parallel to each other. The two sidewalls of the indentation are substantially vertical.
    Type: Application
    Filed: August 7, 2024
    Publication date: July 3, 2025
    Inventor: WEI-YU CHEN
  • Publication number: 20250218859
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an indentation inwardly positioned in the substrate and including a bottom surface and two sidewalls; a catalytic conductive layer positioned on the bottom surface of the indentation. The bottom surface of the indentation and a top surface of the substrate are parallel to each other. The two sidewalls of the indentation are substantially vertical.
    Type: Application
    Filed: January 2, 2024
    Publication date: July 3, 2025
    Inventor: WEI-YU CHEN
  • Publication number: 20250218791
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an indentation inwardly positioned in the substrate and including a bottom surface and two sidewalls; a catalytic conductive layer positioned on the bottom surface of the indentation. The bottom surface of the indentation and a top surface of the substrate are parallel to each other. The two sidewalls of the indentation are substantially vertical.
    Type: Application
    Filed: January 16, 2024
    Publication date: July 3, 2025
    Inventor: WEI-YU CHEN
  • Publication number: 20250218799
    Abstract: A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die.
    Type: Application
    Filed: March 21, 2025
    Publication date: July 3, 2025
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen
  • Patent number: 12344781
    Abstract: A method for preparing a carbon nanodot-fluorescent polymer composite includes subjecting a reactant and a biological component to a reaction at 260° C. to 290° C., so as to obtain the carbon nanodot-fluorescent polymer composite containing a polymer and carbon nanodots dispersed in the polymer. The biological component includes at least one of collagen, chitin, gelatin, and sodium alginate. The reactant is selected from a reaction component or a polycondensate formed therefrom. The reaction component includes terephthalic acid and ethylene glycol capable of reacting with carboxylic acid groups of the terephthalic acid. Also disclosed are the carbon nanodot-fluorescent polymer composite and a carbon nanodot-fluorescent composite fiber including the same.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: July 1, 2025
    Assignee: TAINAN SPINNING CO., LTD.
    Inventors: Wei-Yu Chen, Ya-Yun Ho, Cheng-Ho Chen, Zong-Han Wu, Chia-Yang Wu, Yen-Chou Chen
  • Patent number: 12347802
    Abstract: A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: July 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-Yu Chen, Chi-Yang Yu, Kuan-Lin Ho, Chin-Liang Chen, Yu-Min Liang, Jiun Yi Wu
  • Patent number: 12346694
    Abstract: A processing apparatus includes a general-purpose parallel processing engine including a set of multiple processing elements including a single precision floating-point unit, a double precision floating point unit, and an integer unit; a matrix accelerator including one or more systolic arrays; a first register file coupled with a first read control circuit, wherein the first read control circuit couples with the set of multiple processing elements and the matrix accelerator to arbitrate read requests to the first register file from the set of multiple processing elements and the matrix accelerator; and a second register file coupled with a second read control circuit, wherein the second read control circuit couples with the matrix accelerator to arbitrate read requests to the second register file from the matrix accelerator and limit access to the second register file by the set of multiple processing elements.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: July 1, 2025
    Assignee: Intel Corporation
    Inventors: Chandra Gurram, Wei-yu Chen, Fangwen Fu, Sabareesh Ganapathy, Varghese George, Guei-Yuan Lueh, Subramaniam Maiyuran, Mike Macpherson, Supratim Pal, Jorge Parra
  • Patent number: 12347749
    Abstract: In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.
    Type: Grant
    Filed: June 27, 2023
    Date of Patent: July 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Der-Chyang Yeh, Li-Hsien Huang, Ming Shih Yeh
  • Publication number: 20250201621
    Abstract: A workpiece holder includes a chuck body and a seal ring. The chuck body includes a receiving surface configured to receive a workpiece and at least one vacuum port configured to apply a vacuum seal. The seal ring surrounds a side surface of the chuck body. A top surface of the seal ring is higher than the receiving surface of the chuck body, and the workpiece leans against the seal ring when the vacuum seal is applied between the workpiece and the chuck body.
    Type: Application
    Filed: March 2, 2025
    Publication date: June 19, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Shiuan Wong, Chih-Chiang Tsao, Chao-Wei Chiu, Hao-Jan Pei, Wei-Yu Chen, Hsiu-Jen Lin, Ching-Hua Hsieh, Chia-Shen Cheng
  • Publication number: 20250199858
    Abstract: Provision of multiple register allocation sizes for threads is described. An example of a system includes one or more processors including a graphics processor, the graphics processor including at least a first local thread dispatcher (TDL) and multiple processing resources, each processing resource including a plurality of registers; and memory for storage of data for processing, wherein the one or more processors are to determine a register size for a first thread; identify one or more processing resources having sufficient register space for the first thread; select a processing resource of the one or more processing resources having sufficient register space to assign the first thread; select an available thread slot of the selected processing resource for the first thread; and allocate registers of the selected processing resource for the first thread.
    Type: Application
    Filed: November 25, 2024
    Publication date: June 19, 2025
    Applicant: Intel Corporation
    Inventors: Chandra Gurram, Wei-Yu Chen, Vikranth Vemulapalli, Subramaniam Maiyuran, Jorge Eduardo Parra Osorio, Shuai Mu, Guei-Yuan Lueh, Supratim Pal
  • Patent number: 12327819
    Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: June 10, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen, Ying-Ju Chen, Tsung-Shu Lin, Chin-Chuan Chang, Hsien-Wei Chen, Wei-Cheng Wu, Li-Hsien Huang, Chi-Hsi Wu, Der-Chyang Yeh
  • Patent number: 12299766
    Abstract: Systems and methods for supporting generic pointers in hardware of a graphics processing unit (GPU) are provided. In various examples, a GPU includes multiple sub-cores each having a processing resource and a load/store pipeline. The processing resource is operable to receive a memory access message including a pointer and a memory type identifier indicative of the pointer representing a generic pointer. The processing resource is further operable to output a load or store operation to the load/store pipeline based on the memory access message, including computing an address for the load or store operation by adding a base address of a named memory type of a plurality of named memory types referenced by the generic pointer to an offset into a memory of the named memory type. The load/store pipeline is operable to, responsive to receipt of the load or store operation, access the memory at the address.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: May 13, 2025
    Assignee: Intel Corporation
    Inventors: Joydeep Ray, Prathamesh Raghunath Shinde, Ben J. Ashbaugh, Wei-Yu Chen, Abhishek R. Appu, Vasanth Ranganathan, Dmitry Yurievich Babokin, Ankur N. Shah
  • Publication number: 20250149488
    Abstract: In an embodiment, a method includes forming a device region along a first substrate; forming an interconnect structure over the device region and the first substrate; forming a metal pillar over the interconnect structure, forming the metal pillar comprising: forming a base layer over the interconnect structure; forming an intermediate layer over the base layer; and forming a capping layer over the intermediate layer; forming a solder region over the capping layer; and performing an etch process to recess sidewalls of the base layer and the capping layer from sidewalls of the intermediate layer and the solder region.
    Type: Application
    Filed: February 23, 2024
    Publication date: May 8, 2025
    Inventors: Wei-Yu Chen, Chao-Wei Chiu, Hsin Liang Chen, Hao-Jan Shih, Hao-Jan Pei, Hsiu-Jen Lin
  • Publication number: 20250140757
    Abstract: A chip package structure is provided. The chip package structure includes a wiring structure. The chip package structure includes a first chip structure over the wiring structure. The chip package structure includes a first molding layer surrounding the first chip structure. The chip package structure includes a second chip structure over the first chip structure and the first molding layer. The chip package structure includes a second molding layer surrounding the second chip structure and over the first chip structure and the first molding layer. The chip package structure includes a third chip structure over the second chip structure and the second molding layer. The chip package structure includes a third molding layer surrounding the third chip structure and over the second chip structure and the second molding layer. The chip package structure includes a fourth molding layer surrounding the second molding layer and the third molding layer.
    Type: Application
    Filed: December 31, 2024
    Publication date: May 1, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yu CHEN, An-Jhih SU
  • Patent number: 12282429
    Abstract: An apparatus includes a processor core and a memory hierarchy. The memory hierarchy includes main memory and one or more caches between the main memory and the processor core. A plurality of hardware pre-fetchers are coupled to the memory hierarchy and a pre-fetch control circuit is coupled to the plurality of hardware pre-fetchers. The pre-fetch control circuit is configured to compare changes in one or more cache performance metrics over two or more sampling intervals and control operation of the plurality of hardware pre-fetchers in response to a change in one or more performance metrics between at least a first sampling interval and a second sampling interval.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: April 22, 2025
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Elnaz Ebrahimi, Ehsan Khish Ardestani Zadeh, Wei-Yu Chen, Liang Peng
  • Patent number: 12283492
    Abstract: A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die.
    Type: Grant
    Filed: January 2, 2024
    Date of Patent: April 22, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen