Abstract: A correlated double sampling unit within a CMOS imager employs an image sensor having a plurality of photodetectors arranged in a series of rows and columns with a row addressing circuit, a column addressing circuit, a first sample and hold circuit allocated for each of the columns, a transfer circuit operatively connecting each of the columns to the first sample and hold circuit for each of the columns, and a plurality of second sample and hold circuits, each of the second sample and hold circuits being operatively connected to a subset of the first sample and hold circuits.

Abstract: A CMOS imager is arranged in a plurality of rows and columns with a gain compensation circuit supplied for each of the column. The gain compensation circuit has a first source follower circuit that employs majority carriers of a first polarity yielding a first voltage gain, and a second source follower circuit employing majority carriers of second polarity opposite the first polarity yielding a voltage gain that is essentially the opposite of the first voltage gain variation as compared to the input voltage. The input to the second source follower circuit that is electrically coupled to the output of the second source follower circuit resulting in a gain compensation between the first and second source follower circuits. A selection circuit is configured to enable the gain compensation circuit upon activation of a column select signal.