Patents by Inventor Weldon M. Hanson
Weldon M. Hanson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948602Abstract: Example control circuitry, data storage devices, and methods to provide a spiral data track format that is different from the underlying servo track format are described. The data storage device may include a storage medium configured with a plurality of tracks in at least one continuous spiral pattern and a head actuated over the storage medium. The data tracks may be written to the storage medium with track lengths that are different than a single revolution of the storage medium.Type: GrantFiled: June 29, 2022Date of Patent: April 2, 2024Assignee: Western Digital Technologies, Inc.Inventors: Weldon M. Hanson, Richard Galbraith, Iouri Oboukhov, Niranjay Ravindran, Derrick Burton
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Publication number: 20240106461Abstract: Example channel circuits, data storage devices, and methods for using an adjustable code rate based on an extendable parity code matrix based on write verification determining extended parity are described. A data unit with a base set of parity bits may be written to a non-volatile storage medium and then read back for write verification. The data unit may be decoded using the base set of parity bits and corresponding primary parity matrix. Based on the decoding of the write verification read signal, a number of parity bits for an extended set of parity bits may be determined and the extended set of parity bits may be stored to an extended parity storage location for use during subsequent read operations.Type: ApplicationFiled: September 26, 2022Publication date: March 28, 2024Inventors: Iouri Oboukhov, Derrick E. Burton, Weldon M. Hanson, Niranjay Ravindran, Richard Galbraith, Jonas Goode
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Publication number: 20240097696Abstract: Example channel circuits, data storage devices, and methods for asynchronous sampling from an oversampled analog-to-digital converter are described. The channel circuit may include an analog-to-digital converter configured to generate an oversampled digital signal from an analog data signal using a sample rate that is an integer multiple of the baud rate of the channel circuit. A digital sample interpolator may then interpolate interpolated digital signal values from multiple signal values of the oversampled digital signal and select values at baud rate to generate a baud rate digital signal. The baud rate digital signal may be used by an iterative detector in a timing loop and, once a target timing is achieved, for the iterative detector to detect data bits from the interpolated digital signal.Type: ApplicationFiled: July 18, 2023Publication date: March 21, 2024Inventors: Richard Galbraith, Michael J. Ross, Weldon M. Hanson, John T. Contreras, Iouri Oboukhov, Niranjay Ravindran, Pradhan Bellam, Derrick E. Burton
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Patent number: 11929093Abstract: Example read channel circuits, data storage devices, and methods to provide overlapping processing of data tracks are described. The data storage device may include media configured with a plurality of tracks in a concentric or continuous pattern. The read signal for a data track may be processed using error correction codes (ECC) as it is read during a first track read operation period. Some portion of its data sectors may need additional ECC postprocessing after the first track is initially received and processed by the read channel circuit. While the read signal for a next data track is being read and processed, the read channel circuit may continue postprocessing of the portion of data sectors from the first track during the second track read operations. Various decision parameters for managing the data stream, additional postprocessing time, and rereading tracks for data recovery are also described.Type: GrantFiled: March 22, 2022Date of Patent: March 12, 2024Assignee: Western Digital Technologies, Inc.Inventors: Weldon M. Hanson, Niranjay Ravindran, Richard Galbraith, Iouri Oboukhov
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Publication number: 20240005959Abstract: Example control circuitry, data storage devices, and methods to provide a spiral data track format that is different from the underlying servo track format are described. The data storage device may include a storage medium configured with a plurality of tracks in at least one continuous spiral pattern and a head actuated over the storage medium. The data tracks may be written to the storage medium with track lengths that are different than a single revolution of the storage medium.Type: ApplicationFiled: June 29, 2022Publication date: January 4, 2024Inventors: Weldon M. Hanson, Richard Galbraith, Iouri Oboukhov, Niranjay Ravindran, Derrick Burton
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Publication number: 20230393937Abstract: Example channel circuits, data storage devices, and methods for using an adjustable code rate based on an extendable parity code matrix are described. Data units may be read from a storage medium. Multiple sets of parity bits may be available for different data units, different sets of parity bits having a different number of parity bits corresponding to different parity matrices and desired code rates. A primary parity matrix may provide a base code rate and one or more extended parity matrices may provide increased code rates based on additional rows for increased decoding. Error correction code (ECC) decoding may be selectively performed based on the different sets of parity bits and corresponding parity matrices, resulting in the output of a decoded data units based on the data units from the read signal.Type: ApplicationFiled: June 7, 2022Publication date: December 7, 2023Inventors: Iouri Oboukhov, Derrick Burton, Weldon M. Hanson, Richard Galbraith, Niranjay Ravindran
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Publication number: 20230335158Abstract: Various illustrative aspects are directed to a data storage device comprising data tracks N and N?1, and one or more processing devices, configured to identify, during a track write on the data track N, a write abort event based upon an expected risk for the data track N?1 exceeding a risk threshold, read one or more sectors of the data track N?1 and collect one or more corresponding sector metrics, verify the one or more sectors based upon the collected sector metrics, wherein the verifying comprises assigning each of the one or more sectors as one of a readable or a non-readable sector, and continue the track write on the data track N upon determining each of the one or more sectors is a readable sector, or recovering and relocating the data track N?1 based on determining at least one of the sectors is a non-readable sector.Type: ApplicationFiled: April 18, 2022Publication date: October 19, 2023Inventors: Niranjay Ravindran, Weldon M. Hanson, Hiroyasu Masuda, David T. Flynn, Zarko Popov
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Publication number: 20230307000Abstract: Example read channel circuits, data storage devices, and methods to provide overlapping processing of data tracks are described. The data storage device may include media configured with a plurality of tracks in a concentric or continuous pattern. The read signal for a data track may be processed using error correction codes (ECC) as it is read during a first track read operation period. Some portion of its data sectors may need additional ECC postprocessing after the first track is initially received and processed by the read channel circuit. While the read signal for a next data track is being read and processed, the read channel circuit may continue postprocessing of the portion of data sectors from the first track during the second track read operations. Various decision parameters for managing the data stream, additional postprocessing time, and rereading tracks for data recovery are also described.Type: ApplicationFiled: March 22, 2022Publication date: September 28, 2023Inventors: Weldon M. Hanson, Niranjay Ravindran, Richard Galbraith, Iouri Oboukhov
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Publication number: 20230306994Abstract: Various illustrative aspects are directed to a data storage device comprising data tracks N and N?1, and one or more processing devices, configured to measure signal to noise ratio (SNR) metrics for corresponding sectors of at least one of the data tracks N?1 and N, where the measuring is based at least in part on reading one or more of the data tracks N and N?1 using one or more read offsets, estimate a position of at least one of the data tracks based on measuring the one or more SNR metrics, and reconstruct one or more of risk values for at least a portion of the data track N?1 based on the one or more SNR metrics for the data track N?1, and a position error signal (PES) for at least one of the data tracks N?1 and N based on the corresponding estimated positions.Type: ApplicationFiled: March 24, 2022Publication date: September 28, 2023Inventors: Weldon M. Hanson, Alain Chahwan, Niranjay Ravindran
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Patent number: 11764813Abstract: Example channel circuits, data storage devices, and methods for using an extendable parity code matrix are described. A data unit may be read from a storage medium. Multiple sets of parity bits may be available for the data unit, each set of parity bits having a different number of parity bits corresponding to different parity matrices, including a primary parity matrix and at least one extended parity matrix. The extended parity matrix includes the primary parity matrix and additional rows for increased decoding. Error correction code (ECC) decoding may be selectively performed based on the different sets of parity bits and corresponding parity matrices, resulting in the output of a decoded data unit based on the data unit from the read signal.Type: GrantFiled: June 7, 2022Date of Patent: September 19, 2023Assignee: Western Digital Technologies, Inc.Inventors: Iouri Oboukhov, Derrick Burton, Weldon M. Hanson, Richard Galbraith, Niranjay Ravindran
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Patent number: 11756581Abstract: Various illustrative aspects are directed to a data storage device comprising data tracks N and N?1, and one or more processing devices, configured to measure signal to noise ratio (SNR) metrics for corresponding sectors of at least one of the data tracks N?1 and N, where the measuring is based at least in part on reading one or more of the data tracks N and N?1 using one or more read offsets, estimate a position of at least one of the data tracks based on measuring the one or more SNR metrics, and reconstruct one or more of risk values for at least a portion of the data track N?1 based on the one or more SNR metrics for the data track N?1, and a position error signal (PES) for at least one of the data tracks N?1 and N based on the corresponding estimated positions.Type: GrantFiled: March 24, 2022Date of Patent: September 12, 2023Assignee: Western Digital Technologies, Inc.Inventors: Weldon M. Hanson, Alain Chahwan, Niranjay Ravindran
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Patent number: 11716097Abstract: Example systems, read channel circuits, data storage devices, and methods to provide signal correction based on soft information in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector, and a signal correction circuit. The soft output detector passes detected data bits and corresponding soft information to the signal correction circuit. The signal correction circuit uses the soft information to determine a signal correction value, which is combined with input signal to return a corrected signal to the soft output detector for a next iteration. In some configurations, the signal correction value may compensate for DC offset, AC coupling poles, and/or signal asymmetries to reduce baseline wander in the read channel.Type: GrantFiled: December 29, 2021Date of Patent: August 1, 2023Assignee: Western Digital Technologies, Inc.Inventors: Richard Galbraith, Niranjay Ravindran, Iouri Oboukhov, Pradhan Bellam, Henry Yip, Jonas Goode, Weldon M. Hanson
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Publication number: 20230208445Abstract: Example systems, read channel circuits, data storage devices, and methods to provide signal correction based on soft information in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector, and a signal correction circuit. The soft output detector passes detected data bits and corresponding soft information to the signal correction circuit. The signal correction circuit uses the soft information to determine a signal correction value, which is combined with input signal to return a corrected signal to the soft output detector for a next iteration. In some configurations, the signal correction value may compensate for DC offset, AC coupling poles, and/or signal asymmetries to reduce baseline wander in the read channel.Type: ApplicationFiled: December 29, 2021Publication date: June 29, 2023Inventors: Richard Galbraith, Niranjay Ravindran, Iouri Oboukhov, Pradhan Bellam, Henry Yip, Jonas Goode, Weldon M. Hanson
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Patent number: 11482247Abstract: A data storage device is disclosed comprising a head actuated over a magnetic media comprising a plurality of tracks. A first pattern of magnetic transitions is written to a first segment of a first track. Preparation is made to write a second pattern of magnetic transitions to a second segment of a second track adjacent the first segment of the first track. When the second pattern matches the first pattern, a write boost is configured to a first setting, and when the second pattern does not match the first pattern, the write boost is configured to a second setting. The second pattern of magnetic transitions is then written to the second segment of the second track using the configured write boost.Type: GrantFiled: February 23, 2021Date of Patent: October 25, 2022Assignee: Western Digital Technologies, Inc.Inventors: Guoxiao Guo, Charles A. Park, David Scott C. Amiss, Duc H. Banh, Joey M. Poss, Weldon M. Hanson
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Publication number: 20220246173Abstract: A data storage device is disclosed comprising a head actuated over a magnetic media comprising a plurality of tracks. A first pattern of magnetic transitions is written to a first segment of a first track. Preparation is made to write a second pattern of magnetic transitions to a second segment of a second track adjacent the first segment of the first track. When the second pattern matches the first pattern, a write boost is configured to a first setting, and when the second pattern does not match the first pattern, the write boost is configured to a second setting. The second pattern of magnetic transitions is then written to the second segment of the second track using the configured write boost.Type: ApplicationFiled: February 23, 2021Publication date: August 4, 2022Inventors: Guoxiao Guo, Charles A. Park, David Scott C. Amiss, Duc H. Banh, Joey M. Poss, Weldon M. Hanson
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Patent number: 11386927Abstract: A data storage device configured to access a magnetic tape is disclosed comprising a plurality of data tracks. A first head is configured to access a first data track comprising a first sync mark, and a second head is configured to access a second data track comprising a second sync mark. The first head is used to read first data from the first data track, wherein the first data comprises a plurality of symbols, and the second head is used to read the second sync mark from the second data track. The first data is symbol synchronized based on the second head reading the second sync mark from the second data track.Type: GrantFiled: May 26, 2021Date of Patent: July 12, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Derrick E. Burton, Weldon M. Hanson, Richard L. Galbraith, Iouri Oboukhov
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Patent number: 11373682Abstract: A data storage device is disclosed comprising at least one head configured to access a magnetic tape. The head is used to write contiguously to the magnetic tape a first preamble, followed by a first sync mark, followed by symbols of a first data sector, followed by a second sync mark, followed by a second preamble, followed by a third sync mark, followed by symbols of a second data sector.Type: GrantFiled: February 17, 2021Date of Patent: June 28, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: James N. Malina, Weldon M. Hanson, Derrick E. Burton
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Patent number: 11289123Abstract: An external servo writer configured to write a plurality of embedded servo sectors on a magnetic tape to define a plurality of data tracks is disclosed. A first part of the plurality of embedded servo sectors is written while controlling an actuator to first move a head vertically along a width of the magnetic tape. A second part of the plurality of embedded servo sectors is written while controlling the actuator to second move the head vertically along the width of the magnetic tape.Type: GrantFiled: June 17, 2021Date of Patent: March 29, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Richard L. Galbraith, Weldon M. Hanson, Derrick E. Burton, Niranjay Ravindran, Iouri Oboukhov
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Publication number: 20220068308Abstract: A data storage device is disclosed comprising at least one head configured to access a magnetic tape. The head is used to write contiguously to the magnetic tape a first preamble, followed by a first sync mark, followed by symbols of a first data sector, followed by a second sync mark, followed by a second preamble, followed by a third sync mark, followed by symbols of a second data sector.Type: ApplicationFiled: February 17, 2021Publication date: March 3, 2022Inventors: James N. Malina, Weldon M. Hanson, Derrick E. Burton
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Patent number: 11200912Abstract: A data storage device is disclosed comprising a head actuated over a magnetic media. A write boost is configured to a first setting, and a first pattern of magnetic transitions is written to a first servo field of a servo sector on the magnetic media using the first setting for the write boost. The write boost is configured to a second setting different from the first setting, and the first pattern of magnetic transitions is written to a second servo field of the servo sector on the magnetic media using the second setting for the write boost.Type: GrantFiled: February 23, 2021Date of Patent: December 14, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Guoxiao Guo, Charles A. Park, David Scott C. Amiss, Duc H. Banh, Joey M. Poss, Weldon M. Hanson