Patents by Inventor Weldon M. Hanson

Weldon M. Hanson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210350825
    Abstract: An external servo writer configured to write a plurality of embedded servo sectors on a magnetic tape to define a plurality of data tracks is disclosed. A first part of the plurality of embedded servo sectors is written while controlling an actuator to first move a head vertically along a width of the magnetic tape. A second part of the plurality of embedded servo sectors is written while controlling the actuator to second move the head vertically along the width of the magnetic tape.
    Type: Application
    Filed: June 17, 2021
    Publication date: November 11, 2021
    Inventors: RICHARD L. GALBRAITH, WELDON M. HANSON, DERRICK E. BURTON, NIRANJAY RAVINDRAN, IOURI OBOUKHOV
  • Patent number: 11138996
    Abstract: A data storage device is disclosed comprising at least one head configured to access a magnetic tape comprising a plurality of data tracks, wherein each data track comprises a plurality of data segments and a plurality of servo sectors. The head is used to read one of the servo sectors to generate a first read signal. The first read signal is processed to generate a position error signal (PES) of the head relative to the magnetic tape, wherein the head is positioned relative to the magnetic tape based on the PES. The head is used to read one of the data segments to generate a second read signal, wherein the second read signal is processed to detect user data recorded in the data segment.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: October 5, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Richard L. Galbraith, Weldon M. Hanson, Derrick E. Burton, Niranjay Ravindran, Iouri Oboukhov
  • Patent number: 11055171
    Abstract: A data storage device is disclosed comprising a head actuated over a disk. A first plurality of codewords and corresponding parity sector are generated, and a second plurality of codewords and corresponding parity sector are generated. The first and second plurality of codewords are written to the disk, and during a read of the first and second set of codewords, M codeword locations within the data track that are unrecoverable are saved, and N codeword locations out of the M codeword locations are selected based on a quality metric of the read. The N codewords are reread from the data track at the N codeword locations and reliability metrics associated with the N codewords are saved. The saved reliability metrics are updated using at least one of the first parity sector or the second parity sector.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: July 6, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Niranjay Ravindran, Weldon M. Hanson, Richard L. Galbraith, David T. Flynn, Iouri Oboukhov
  • Patent number: 11049520
    Abstract: A data storage device is disclosed comprising at least one head configured to access a magnetic tape. Data is read from the magnetic tape to generate a read signal which is processed to decode a first M blocks of low density parity check (LDPC) type codewords using a LDPC type decoder. First un-converged codewords out of the first M blocks are decoded using a first M-blocks parity, and second un-converged codewords out of the first M blocks are decoded using an erasure code.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: June 29, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Richard L. Galbraith, Weldon M. Hanson, Derrick E. Burton, Niranjay Ravindran, Iouri Oboukhov
  • Patent number: 10783913
    Abstract: A data storage device is disclosed comprising a head actuated over a disk surface, wherein the head comprises a plurality of elements including a write assist element. A bias signal applied to the write assist element is controlled such that the write assist element is substantially unprotruded, and while the write element is substantially unprotruded, an air bearing resonant frequency (ABRF) of the head and disk surface is measured. The bias signal applied to the write assist element is controlled such that the write assist element protrudes toward the disk surface, and while the write assist element protrudes toward the disk surface, the head is excited at the measured ABRF and the head touching down onto the disk surface is detected.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 22, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sukumar Rajauria, Erhard Schreck, Weldon M. Hanson, Yeoungchin Yoon
  • Patent number: 10748567
    Abstract: A data storage device is disclosed comprising a head actuated over a disk comprising a plurality of data tracks, including consecutive data tracks N?1 and N. A first write to data track N is performed using a first position error signal (PES) representing a position of the head relative to the data tracks. A track squeeze metric is generated for data track N?1 based on at least the first PES of the first write. The track squeeze metric for data track N?1 is accumulated during the first write, and the first write is aborted when the accumulated track squeeze metric for data track N?1 exceeds a first threshold.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: August 18, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Hideki Zaitsu, Niranjay Ravindran, So Ogiwara, Toshihisa Komai, Alain Chahwan, Weldon M. Hanson
  • Publication number: 20200210277
    Abstract: A data storage device is disclosed comprising a head actuated over a disk. A first plurality of codewords and corresponding parity sector are generated, and a second plurality of codewords and corresponding parity sector are generated. The first and second plurality of codewords are written to the disk, and during a read of the first and second set of codewords, M codeword locations within the data track that are unrecoverable are saved, and N codeword locations out of the M codeword locations are selected based on a quality metric of the read. The N codewords are reread from the data track at the N codeword locations and reliability metrics associated with the N codewords are saved. The saved reliability metrics are updated using at least one of the first parity sector or the second parity sector.
    Type: Application
    Filed: March 11, 2020
    Publication date: July 2, 2020
    Inventors: NIRANJAY RAVINDRAN, WELDON M. HANSON, RICHARD L. GALBRAITH, DAVID T. FLYNN, IOURI OBOUKHOV
  • Patent number: 10606699
    Abstract: A data storage device is disclosed wherein a first plurality of codewords are generated each comprising a plurality of symbols, and a first parity sector is generated over the first plurality of codewords. A second plurality of codewords are generated each comprising a plurality of symbols, and a second parity sector is generated over the second plurality of codewords. A third parity sector is generated over a first subset of the first plurality of codewords and a first subset of the second plurality of codewords, and a fourth parity sector is generated over a second subset of the first plurality of codewords and a second subset of the second plurality of codewords. When processing of a first codeword fails, the first codeword and the first parity sector are processed using a LDPC type decoder, and the first codeword and the third parity sector are processed using the LDPC type decoder.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: March 31, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Iouri Oboukhov, Weldon M. Hanson, Niranjay Ravindran, David T. Flynn
  • Patent number: 10530390
    Abstract: A data storage device is disclosed comprising a head actuated over a disk comprising a data track having at least a first data segment and a second data segment. A first plurality of codewords are generated, and a first parity sector is generated over the first plurality of codewords. The first plurality of codewords and the first parity sector are written to the first data segment. A second plurality of codewords are generated, and a second parity sector is generated over the second plurality of codewords. The second plurality of codewords and the second parity sector are written to the second data segment. During a read operation the data segments of the data track are processed sequentially to decode the codewords using a low density parity check (LDPC) decoder, wherein the reliability metrics of un-converged codewords are stored in a codeword buffer and updated using the respective parity sector.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: January 7, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Iouri Oboukhov, Weldon M. Hanson, Niranjay Ravindran, Richard L. Galbraith
  • Publication number: 20190356334
    Abstract: A data storage device is disclosed comprising a head actuated over a disk comprising a data track having at least a first data segment and a second data segment. A first plurality of codewords are generated, and a first parity sector is generated over the first plurality of codewords. The first plurality of codewords and the first parity sector are written to the first data segment. A second plurality of codewords are generated, and a second parity sector is generated over the second plurality of codewords. The second plurality of codewords and the second parity sector are written to the second data segment. During a read operation the data segments of the data track are processed sequentially to decode the codewords using a low density parity check (LDPC) decoder, wherein the reliability metrics of un-converged codewords are stored in a codeword buffer and updated using the respective parity sector.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 21, 2019
    Inventors: IOURI OBOUKHOV, WELDON M. HANSON, NIRANJAY RAVINDRAN, RICHARD L. GALBRAITH
  • Publication number: 20190354434
    Abstract: A data storage device is disclosed wherein a first plurality of codewords are generated each comprising a plurality of symbols, and a first parity sector is generated over the first plurality of codewords. A second plurality of codewords are generated each comprising a plurality of symbols, and a second parity sector is generated over the second plurality of codewords. A third parity sector is generated over a first subset of the first plurality of codewords and a first subset of the second plurality of codewords, and a fourth parity sector is generated over a second subset of the first plurality of codewords and a second subset of the second plurality of codewords. When processing of a first codeword fails, the first codeword and the first parity sector are processed using a LDPC type decoder, and the first codeword and the third parity sector are processed using the LDPC type decoder.
    Type: Application
    Filed: January 10, 2019
    Publication date: November 21, 2019
    Inventors: IOURI OBOUKHOV, WELDON M. HANSON, NIRANJAY RAVINDRAN, DAVID T. FLYNN
  • Patent number: 10417089
    Abstract: A data storage device is disclosed comprising a non-volatile storage medium (NVSM). A reliability metric for each symbol of each of a plurality of codewords read from the NVSM is generated, and a number of erasures for a first codeword are generated, wherein the number of erasures exceeds the correction power of the first codeword. A reliability metric of the first codeword is modified corresponding to one of the erasures. The reliability metrics for each codeword including the modified reliability metrics of the first codeword are first iteratively processed using a low density parity check (LDPC) type decoder, thereby first updating the reliability metric for each symbol of each codeword. The reliability metrics for the first codeword are second updated using the parity sector, and the second updated reliability metrics for the first codeword are second iteratively processed using the LDPC-type decoder.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: September 17, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Iouri Oboukhov, Weldon M. Hanson, Niranjay Ravindran, Richard L. Galbraith
  • Publication number: 20190250987
    Abstract: A data storage device is disclosed comprising a non-volatile storage medium (NVSM). A reliability metric for each symbol of each of a plurality of codewords read from the NVSM is generated, and a number of erasures for a first codeword are generated, wherein the number of erasures exceeds the correction power of the first codeword. A reliability metric of the first codeword is modified corresponding to one of the erasures. The reliability metrics for each codeword including the modified reliability metrics of the first codeword are first iteratively processed using a low density parity check (LDPC) type decoder, thereby first updating the reliability metric for each symbol of each codeword. The reliability metrics for the first codeword are second updated using the parity sector, and the second updated reliability metrics for the first codeword are second iteratively processed using the LDPC-type decoder.
    Type: Application
    Filed: February 13, 2018
    Publication date: August 15, 2019
    Inventors: IOURI OBOUKHOV, WELDON M. HANSON, NIRANJAY RAVINDRAN, RICHARD L. GALBRAITH
  • Patent number: 10373645
    Abstract: A data storage device is disclosed wherein a first codeword is generated comprising first redundancy, and a second codeword is generated comprising second redundancy. At least part of the first codeword is written to a first data sector and a second data sector of a first data track on a disk, and at least part of the second codeword is written to a third data sector and a fourth data sector of the first data track different from the first data sector and the second data sector. When an anomaly is detected in the first data sector, first extended redundancy is generated over at least the first data sector and the second data sector of the first data track without generating second extended redundancy over the third data sector and the fourth data sector. Data is recovered from the first data sector based on the first extended redundancy.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: August 6, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Derrick E. Burton, Weldon M. Hanson
  • Publication number: 20190156861
    Abstract: A data storage device is disclosed wherein a first codeword is generated comprising first redundancy, and a second codeword is generated comprising second redundancy. At least part of the first codeword is written to a first data sector and a second data sector of a first data track on a disk, and at least part of the second codeword is written to a third data sector and a fourth data sector of the first data track different from the first data sector and the second data sector. When an anomaly is detected in the first data sector, first extended redundancy is generated over at least the first data sector and the second data sector of the first data track without generating second extended redundancy over the third data sector and the fourth data sector. Data is recovered from the first data sector based on the first extended redundancy.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 23, 2019
    Inventors: Derrick E. Burton, Weldon M. Hanson
  • Patent number: 9632863
    Abstract: In general, techniques are described for performing track-error-correcting code on data. A hard drive comprising a storage device and a read channel may be configured to perform the techniques. The read channel may be configured to read data from a track comprising a plurality of data sectors each comprising a plurality of bits, and a parity sector comprising a plurality of parity bits, wherein the data includes a plurality of bit groups, each bit group including a single bit from each data sector, and wherein each parity bit corresponds to a respective bit group, perform a track parity check, and, responsive to determining that the data includes an error, identify one or more data sectors as possible sources of the at least one error and adjust a log-likelihood ratio for at least one bit from the bit group.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: April 25, 2017
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Richard L. Galbraith, Weldon M. Hanson, Roger W. Wood
  • Publication number: 20160203041
    Abstract: In general, techniques are described for performing track-error-correcting code on data. A hard drive comprising a storage device and a read channel may be configured to perform the techniques. The read channel may be configured to read data from a track comprising a plurality of data sectors each comprising a plurality of bits, and a parity sector comprising a plurality of parity bits, wherein the data includes a plurality of bit groups, each bit group including a single bit from each data sector, and wherein each parity bit corresponds to a respective bit group, perform a track parity check, and, responsive to determining that the data includes an error, identify one or more data sectors as possible sources of the at least one error and adjust a log-likelihood ratio for at least one bit from the bit group.
    Type: Application
    Filed: January 13, 2015
    Publication date: July 14, 2016
    Inventors: Richard L. Galbraith, Weldon M. Hanson, Roger W. Wood
  • Patent number: 9361922
    Abstract: Techniques for determining a relative spacing between a read head and a surface of a magnetic data storage device may use at least two magnetic spacing measurement patterns. A first magnetic spacing measurement pattern may be offset from a center of a data track by a first offset value and a second magnetic spacing measurement pattern may be offset by a second, different, offset value. A processor may determine a first harmonic tone and a second harmonic tone from each of the first and second magnetic spacing measurement patterns. The processor also may determine respective ratios between amplitudes of the first and second harmonic tones for each of the first and second magnetic spacing measurement patterns. The processor may determine which ratio is greater, and may utilize the greater ratio when determining relative spacing between the read head and the surface of the magnetic data storage device.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: June 7, 2016
    Assignee: HGST Netherlands B.V.
    Inventors: Weldon M. Hanson, Kazuhiro Saito
  • Patent number: 8276038
    Abstract: A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called preceding to the modulation encoded bit stream. However, this preceding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before preceding is applied by the precoder. The decoder subsystem operates in the inverse manner.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Roy D. Cideciyan, Ajay Dholakia, Evangelos S. Eleftheriou, Richard L. Galbraith, Weldon M. Hanson, Thomas Mittelholzer, Travis R. Oenning
  • Patent number: 7694205
    Abstract: A method and apparatus for providing a read channel having combined parity and non-parity post processing is disclosed. A post-processor combines parity and non-parity post processing to make both parity and non-parity corrections so that error events that cannot be detected by parity may be corrected. Non-parity detectable error events are only kept for consideration if their likelihood is above a set threshold.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: April 6, 2010
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Roy D. Cideciyan, Ajay Dholakia, Evangelos S. Eleftheriou, Richard L. Galbraith, Weldon M. Hanson, Thomas Mittelholzer, Travis R. Oenning