Patents by Inventor Wen-Cheng Wu

Wen-Cheng Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11174520
    Abstract: A method and a kit for detecting mycobacterium are provided. The method includes steps of: providing a sample; providing a pair of primers, which is selected from a group consisting of a sequence having about 45% to 100% similar to SEQ ID NO. 1, a sequence having about 60% to 100% similar to SEQ ID NO. 2, a sequence complementary thereof; performing a polymerase chain reaction by using the set of primers and the sample to obtain a product; and analyzing the product to detect the presence of the mycobacterium.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: November 16, 2021
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chih-Cheng Tsou, Min-Hsien Wu, Wen-Pin Chou, Hsin-Yao Wang, Chien-Ru Lin
  • Patent number: 11169254
    Abstract: An operation mode control method implemented by a radar system, the operation mode control method includes steps of: (S1) receiving a single target tracking (STT) triggering data comprising a representation of triggering of a STT tracking mode and a selected tracking target to be tracked by the radar system; (S2) controlling a radar sensor to emit detection wave beam; (S3) controlling, the radar sensor to receive echo waves; (S4) analyzing, echo signal to generate STT target data; (S5) executing a STT program to obtain a tracking data of a selected tracking target; (S6) outputting the tracking data to a memory device for storage or to a human-machine interface (HMI) device for presenting to the user of the radar system.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: November 9, 2021
    Assignee: NATIONAL CHUNG-SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Shih-Che Tsai, Min-Ching Lin, Kuang-Fu Chung, Chun-Cheng Chen, Ruei-Shen Wang, Po-Ju Chiang, Ming-Jhe Wu, Hung-Fu Chang, Wen-Chin Liao
  • Publication number: 20210327778
    Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.
    Type: Application
    Filed: June 29, 2021
    Publication date: October 21, 2021
    Inventors: Chen-Hua Yu, Wen-Hsin Wei, Chi-Hsi Wu, Shang-Yun Hou, Jing-Cheng Lin, Hsien-Pin Hu, Ying-Ching Shih, Szu-Wei Lu
  • Patent number: 11145713
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Karthick Murukesan, Wen-Chih Chiang, Chun Lin Tsai, Ker-Hsiao Huo, Kuo-Ming Wu, Po-Chih Chen, Ru-Yi Su, Shiuan-Jeng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
  • Patent number: 11105990
    Abstract: The present invention is to provide an optical transceiver module comprising a housing, a substrate, an optical receiving device and a plurality of optical transmitting devices. The substrate is disposed in the housing. The optical receiving device is disposed on the substrate. The plurality of optical transmitting devices are connected to the substrate, and there is a tilt angle between the optical transmitting devices and the substrate.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: August 31, 2021
    Assignee: USENLIGHT CORPORATION
    Inventors: Chun-Yang Chang, Yun-Cheng Huang, Wen-Hsien Li, Cheng-Hung Lu, Ming-Ju Chen, Chang-Cherng Wu
  • Patent number: 10978341
    Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Sun, Han-Ti Hsiaw, Yi-Wei Chiu, Kuan-Cheng Wang, Shin-Yeu Tsai, Jr-Yu Chen, Wen-Cheng Wu
  • Publication number: 20200373154
    Abstract: A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 26, 2020
    Inventors: Dong-Sheng Li, Chia-Hui Lin, Kai Hung Cheng, Yao-Hsu Sun, Wen-Cheng Wu, Bo-Cyuan Lu, Sung-En Lin, Tai-Chun Huang
  • Patent number: 10734227
    Abstract: A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dong-Sheng Li, Chia-Hui Lin, Kai Hung Cheng, Yao-Hsu Sun, Wen-Cheng Wu, Bo-Cyuan Lu, Sung-En Lin, Tai-Chun Huang
  • Publication number: 20200111705
    Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 9, 2020
    Inventors: Chih-Hung Sun, Han-Ti Hsiaw, Yi-Wei Chiu, Kuan-Cheng Wang, Shin-Yeu Tsai, Jr-Yu Chen, Wen-Cheng Wu
  • Publication number: 20200075320
    Abstract: A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin.
    Type: Application
    Filed: June 3, 2019
    Publication date: March 5, 2020
    Inventors: Dong-Sheng Li, Chia-Hui Lin, Kai Hung Cheng, Yao-Hsu Sun, Wen-Cheng Wu, Bo-Cyuan Lu, Sung-En Lin, Tai-Chun Huang
  • Patent number: 10510593
    Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Sun, Han-Ti Hsiaw, Yi-Wei Chiu, Kuan-Cheng Wang, Shin-Yeu Tsai, Jr-Yu Chen, Wen-Cheng Wu
  • Publication number: 20180151425
    Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.
    Type: Application
    Filed: January 12, 2018
    Publication date: May 31, 2018
    Inventors: Chih-Hung Sun, Han-Ti Hsiaw, Yi-Wei Chiu, Kuan-Cheng Wang, Shin-Yeu Tsai, Jr-Yu Chen, Wen-Cheng Wu
  • Patent number: 9881834
    Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: January 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Sun, Han-Ti Hsiaw, Yi-Wei Chiu, Kuan-Cheng Wang, Shin-Yeu Tsai, Jr-Yu Chen, Wen-Cheng Wu
  • Patent number: 9346209
    Abstract: Disclosed are a feedblock multiplier with thickness gradient variation, a feedblock system, a method, and multilayer structure made by the method. The feedblock multiplier combines the functionalities of feedblock and multiplier conventionally used for producing the multilayer structure. The feedblock multiplier includes an input section for feeding fluid materials. A feedblock section is included for dividing the fluid delivered into multiple channels correspondingly. The fluids in the channels are segmented into two or more fluid segments by a segmenting section. The each fluid segment is delivered through corresponding channel-conversion section with thickness-gradient variation in the feedblock multiplier. Each channel-conversion section includes multiple channels with configurable positions. The fluids are then combined in a multiplier section for producing the multilayer structure with overlapped layers. The multilayer structure is outputted from an extruding section.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: May 24, 2016
    Assignee: EXTEND OPTRONICS CORP.
    Inventors: Jen-Huai Chang, Wen-Cheng Wu
  • Publication number: 20160075071
    Abstract: Disclosed are a feedblock multiplier with thickness gradient variation, a feedblock system, a method, and multilayer structure made by the method. The feedblock multiplier combines the functionalities of feedblock and multiplier conventionally used for producing the multilayer structure. The feedblock multiplier includes an input section for feeding fluid materials. A feedblock section is included for dividing the fluid delivered into multiple channels correspondingly. The fluids in the channels are segmented into two or more fluid segments by a segmenting section. The each fluid segment is delivered through corresponding channel-conversion section with thickness-gradient variation in the feedblock multiplier. Each channel-conversion section includes multiple channels with configurable positions. The fluids are then combined in a multiplier section for producing the multilayer structure with overlapped layers. The multilayer structure is outputted from an extruding section.
    Type: Application
    Filed: November 30, 2015
    Publication date: March 17, 2016
    Inventors: JEN-HUAI CHANG, WEN-CHENG WU
  • Patent number: 9227354
    Abstract: Disclosed are a feedblock multiplier with thickness gradient variation, a feedblock system, a method, and multilayer structure made by the method. The feedblock multiplier combines the functionalities of feedblock and multiplier conventionally used for producing the multilayer structure. The feedblock multiplier includes an input section for feeding fluid materials. A feedblock section is included for dividing the fluid delivered into multiple channels correspondingly. The fluids in the channels are segmented into two or more fluid segments by a segmenting section. The each fluid segment is delivered through corresponding channel-conversion section with thickness-gradient variation in the feedblock multiplier. Each channel-conversion section includes multiple channels with configurable positions. The fluids are then combined in a multiplier section for producing the multilayer structure with overlapped layers. The multilayer structure is outputted from an extruding section.
    Type: Grant
    Filed: May 6, 2012
    Date of Patent: January 5, 2016
    Assignee: EXTEND OPTRONICS CORP.
    Inventors: Jen-Huai Chang, Wen-Cheng Wu, Chao-Ying Lin
  • Patent number: 8896705
    Abstract: A measuring device for measuring a response speed of a display panel is provided. The measuring device includes a microcontroller and at least one photo sensor. The microcontroller provides a control command, according to which a display controller of the display panel provides test pattern to the display panel. The photo sensor senses a test frame displayed corresponding to the test pattern by the display panel, and provides a corresponding sensing signal associated with brightness and a response signal. According to the response signal, the response speed of the display panel is calculated.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: November 25, 2014
    Assignee: MStar Semiconductor, Inc.
    Inventors: Chih-Chiang Chiu, Tien-Hua Yu, Wen-Cheng Wu
  • Publication number: 20130300878
    Abstract: A measuring device for measuring a response speed of a display panel is provided. The measuring device includes a microcontroller and at least one photo sensor. The microcontroller provides a control command, according to which a display controller of the display panel provides test pattern to the display panel. The photo sensor senses a test frame displayed corresponding to the test pattern by the display panel, and provides a corresponding sensing signal associated with brightness and a response signal. According to the response signal, the response speed of the display panel is calculated.
    Type: Application
    Filed: August 21, 2012
    Publication date: November 14, 2013
    Applicant: MStar Semiconductor, Inc.
    Inventors: Chih-Chiang Chiu, Tien-Hua Yu, Wen-Cheng Wu
  • Publication number: 20130292871
    Abstract: Disclosed are a feedblock multiplier with thickness gradient variation, a feedblock system, a method, and multilayer structure made by the method. The feedblock multiplier combines the functionalities of feedblock and multiplier conventionally used for producing the multilayer structure. The feedblock multiplier includes an input section for feeding fluid materials. A feedblock section is included for dividing the fluid delivered into multiple channels correspondingly. The fluids in the channels are segmented into two or more fluid segments by a segmenting section. The each fluid segment is delivered through corresponding channel-conversion section with thickness-gradient variation in the feedblock multiplier. Each channel-conversion section includes multiple channels with configurable positions. The fluids are then combined in a multiplier section for producing the multilayer structure with overlapped layers. The multilayer structure is outputted from an extruding section.
    Type: Application
    Filed: May 6, 2012
    Publication date: November 7, 2013
    Applicant: EXTEND OPTRONICS CORP.
    Inventors: Jen-Huai Chang, Wen-Cheng Wu, Chao-Ying Lin
  • Patent number: 8035476
    Abstract: The present invention relates to a chip resistor and method for making the same. The chip resistor includes a substrate, a pair of bottom electrodes, a resistive film, a pair of main upper electrodes, a first protective coat, a pair of barrier layers, a second protective coat, a pair of side electrodes and at least one plated layer. The first protective coat is disposed over the resistive film, and covers part of the main upper electrodes. The barrier layers are disposed on the main upper electrodes, and cover part of the first protective coat. The second protective coat is disposed on the first protective coat, and covers part of the barrier layers. The plated layers cover the barrier layers, the bottom electrodes and the side electrodes. As a result, the chip resistor features high corrosion resistance.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: October 11, 2011
    Assignee: Yageo Corporation
    Inventors: Chih-Chung Yang, Wen-Fon Wu, Mei-Ling Lin, Wen-Cheng Wu, Tsai-Hu Chen, Wen-Hsing Kong