Abstract: A smart motion detection device with a determining method includes a memory, a processor, and a sensor array coupled to the memory and the processor. An image captured by the sensor array is processed by the processor. The sensor array is adapted to pre-store the image into the memory when the processor is operated in the sleep mode, and the pre-stored image is transmitted to the processor when the processor is operated in the wakeup mode. The sensor array includes a comparator adapted to generate an alarm signal for switching the processor from the sleep mode to the wakeup mode in accordance with a comparison result of the pre-stored image. The determining method includes the processor analyzing images captured by the sensor array when the sensor array is activated to capture the images, and the processor analyzing images pre-stored inside the memory when the sensor array is not activated.

Abstract: A digital imaging device including a sensor array, an analog front end and a digital back end. The sensor array is configured to output black pixel data and normal pixel data. The analog front end is configured to amplify the black pixel data and the normal pixel data with a gain, and calibrate the amplified black pixel data and the amplified normal pixel data with a calibration value. The digital back end is configured to digitize the amplified and calibrated black pixel data, calculate a data offset according to digital black pixel data, determine a dynamic adjust scale, calculate the calibration value according to the gain, the data offset and the dynamic adjust scale, and adjust the gain according to the dynamic adjust scale.

Abstract: A digital imaging device including a sensor array, an analog front end and a digital back end. The sensor array is configured to output black pixel data and normal pixel data. The analog front end is configured to amplify the black pixel data and the normal pixel data with a gain, and calibrate the amplified black pixel data and the amplified normal pixel data with a calibration value. The digital back end is configured to digitize the amplified and calibrated black pixel data, calculate a data offset according to digital black pixel data, determine a dynamic adjust scale, calculate the calibration value according to the gain, the data offset and the dynamic adjust scale, and adjust the gain according to the dynamic adjust scale.

Abstract: A method for reducing fixed pattern noise of an image sensor is provided. The method includes: accessing pixel data of at least one test frame in a test environment; and calculating/deriving average values of each column based on at least one portion of pixel data of the column in the at least one test frame, wherein the average values of columns are used as calibration values for calibrating image pixel data of columns when the image sensor operates in a normal light source environment.

Abstract: A method for reducing fixed pattern noise of an image sensor is provided. The method includes: accessing pixel data of at least one test frame in a test environment; and calculating/deriving average values of each column based on at least one portion of pixel data of the column in the at least one test frame, wherein the average values of columns are used as calibration values for calibrating image pixel data of columns when the image sensor operates in a normal light source environment.

Abstract: There is provided a back side illuminated semiconductor structure with a semiconductor capacitor connected to a floating diffusion node in which the semiconductor capacitor for reducing a dimension of the floating diffusion node is provided above the floating diffusion node so as to eliminate the influence thereto by incident light and enhance the light absorption efficiency.

Abstract: A digital imaging device including a sensor array, an analog front end and a digital back end. The sensor array is configured to output black pixel data and normal pixel data. The analog front end is configured to amplify the black pixel data and the normal pixel data with a gain, and calibrate the amplified black pixel data and the amplified normal pixel data with a calibration value. The digital back end is configured to digitize the amplified and calibrated black pixel data, calculate a data offset according to digital black pixel data, determine a dynamic adjust scale, calculate the calibration value according to the gain, the data offset and the dynamic adjust scale, and adjust the gain according to the dynamic adjust scale.

Abstract: There is provided a back side illuminated semiconductor structure with a semiconductor capacitor connected to a floating diffusion node in which the semiconductor capacitor for reducing a dimension of the floating diffusion node is provided above the floating diffusion node so as to eliminate the influence thereto by incident light and enhance the light absorption efficiency.

Abstract: The present invention discloses a high dynamic range imager circuit and a method for reading high dynamic range image with an adaptive conversion gain. The high dynamic range image circuit includes a variable capacitor. The capacitance of the variable capacitor is adjusted according to sensed light intensity or by internal feedback control, to adaptively adjust the conversion gain of the high dynamic range image circuit as it reads a signal which relates to a pixel image sensed by an image sensor device. In each cycle, the signal can be read twice or more with different dynamic ranges, to enhance the accuracy of the signal.

Abstract: An image sensing device and image sensing method is described, in which an interrupt circuit is disposed to interrupt a clock signal input to a logic circuit not associated with the reading of image data when the image data is read, so as to temporarily interrupt the operation of the logic circuit, thereby reducing the power noises caused by the current generated during the operation of the logic circuit.

Abstract: The present invention discloses a high dynamic range imager circuit and a method for reading high dynamic range image with an adaptive conversion gain. The high dynamic range image circuit includes a variable capacitor. The capacitance of the variable capacitor is adjusted according to sensed light intensity or by internal feedback control, to adaptively adjust the conversion gain of the high dynamic range image circuit as it reads a signal which relates to a pixel image sensed by an image sensor device. In each cycle, the signal can be read twice or more with different dynamic ranges, to enhance the accuracy of the signal.

Abstract: An image sensing device and image sensing method is described, in which an interrupt circuit is disposed to interrupt a clock signal input to a logic circuit not associated with the reading of image data when the image data is read, so as to temporarily interrupt the operation of the logic circuit, thereby reducing the power noises caused by the current generated during the operation of the logic circuit.

Abstract: An image sensing device and image sensing method is described, in which an interrupt circuit is disposed to interrupt a clock signal input to a logic circuit not associated with the reading of image data when the image data is read, so as to temporarily interrupt the operation of the logic circuit, thereby reducing the power noises caused by the current generated during the operation of the logic circuit.

Abstract: An image sensing device and image sensing method is described, in which an interrupt circuit is disposed to interrupt a clock signal input to a logic circuit not associated with the reading of image data when the image data is read, so as to temporarily interrupt the operation of the logic circuit, thereby reducing the power noises caused by the current generated during the operation of the logic circuit.

Abstract: Apparatus for configuring network media connections. A medium-dependent interface crossover includes a first input terminal set comprising a first input pair and a first enabling pair, a second input terminal set comprising a second input pair and a second enabling pair, and an output pair selectively outputting data corresponding to data signals received by the first input pair or the second input pair. A detection circuit detects the data, and outputs a selection signal according to the detected data. A selection circuit receives the data signals, and provides the data signals to the first input pair or the second input pair and selects the first enabling pair or the second enabling pair according to the selection signal.

Abstract: Apparatus for configuring network media connections. A medium-dependent interface crossover includes a first input terminal set comprising a first input pair and a first enabling pair, a second input terminal set comprising a second input pair and a second enabling pair, and an output pair selectively outputting data corresponding to data signals received by the first input pair or the second input pair. A detection circuit detects the data, and outputs a selection signal according to the detected data. A selection circuit receives the data signals, and provides the data signals to the first input pair or the second input pair and selects the first enabling pair or the second enabling pair according to the selection signal.

Abstract: A bandgap reference circuit. In the bandgap reference circuit, a current generator includes a first bipolar junction transistor (BJT) and generates a first positive temperature coefficient current thereby producing a negative temperature coefficient voltage between a base terminal and an emitter terminal of the first bipolar junction transistor. A single-end gain amplifier includes a positive input terminal coupled to the emitter terminal of first the bipolar junction transistor. A first resistor is coupled between the output terminal of the single-end gain amplifier and an output terminal of the bandgap reference circuit to generate a first current. A current-to-voltage converter is coupled to the first resistor to convert the first positive temperature coefficient current and the first current to a bandgap voltage.

Abstract: A voltage regulator, regulating a supply voltage and outputting a regulated voltage. The voltage regulator comprises a two stage OP which outputs a first voltage and a second voltage according to a reference voltage and a feedback voltage. A NMOS transistor controlled by a voltage detection unit, to receive the second voltage when the detected supply voltage is in a high mode. A PMOS transistor controlled by the voltage detection unit, to receive the first voltage when the detected supply voltage is in a low mode. A feedback circuit for receiving the regulated voltage and outputting the feedback voltage to the two stage OP.

Abstract: An active matrix LED display driving circuit. The circuit comprises a first transistor having a drain, a source coupled to receive a data signal and a gate coupled to receive a scan signal and, a second transistor having a drain, a source coupled to receive the data signal and a gate coupled to receive the scan signal, a third transistor having a source, a drain coupled to the drain of the second transistor and a gate coupled to the drain of the first transistor, a fourth transistor having a drain coupled to receive a first voltage, and a gate coupled to receive the scan signal and a source coupled to the drain of the second transistor, a light emitting diode having an anode coupled to the source of the third transistor and a cathode coupled to receive a second voltage, and a capacitor coupled between the gate and source of the third transistor.

Abstract: A voltage detection circuit. A second NMOS transistor has a gate coupled to the gate of a first NMOS transistor. A comparator has input terminals, and an output terminal. A first resistor is coupled between the first input terminal and the source of the first NMOS transistor, a second resistor is coupled to the comparator and the first resistor, a third resistor is coupled between the second resistor and the comparator, and a fourth resistor is coupled between the second and third resistors, and ground. A first PMOS transistor has a gate coupled to the gates of the first and second NMOS transistors. A second PMOS transistor has a connected gate and drain, a source coupled to the gates of first and second NMOS transistors, a drain coupled to ground, and an n-well directly connected to the gates of the first and second NMOS transistors.