Abstract: A voltage regulator, regulating a supply voltage and outputting a regulated voltage. The voltage regulator comprises a two stage OP which outputs a first voltage and a second voltage according to a reference voltage and a feedback voltage. A NMOS transistor controlled by a voltage detection unit, to receive the second voltage when the detected supply voltage is in a high mode. A PMOS transistor controlled by the voltage detection unit, to receive the first voltage when the detected supply voltage is in a low mode. A feedback circuit for receiving the regulated voltage and outputting the feedback voltage to the two stage OP.

Abstract: A bandgap reference circuit. In the bandgap reference circuit, a current generator includes a first bipolar junction transistor (BJT) and generates a first positive temperature coefficient current thereby producing a negative temperature coefficient voltage between a base terminal and an emitter terminal of the first bipolar junction transistor. A single-end gain amplifier includes a positive input terminal coupled to the emitter terminal of first the bipolar junction transistor. A first resistor is coupled between the output terminal of the single-end gain amplifier and an output terminal of the bandgap reference circuit to generate a first current. A current-to-voltage converter is coupled to the first resistor to convert the first positive temperature coefficient current and the first current to a bandgap voltage.

Abstract: A fast start up oscillator. The fast start-up oscillator includes a power-on-reset detect circuit, a bandgap circuit, a voltage detect circuit, a RC-oscillator, and a count two circuit. The fast start-up oscillator is provided with a fast stabilized voltage source to ensure oscillation accurate and quickly such that the system is woken up.

Abstract: A reference voltage providing circuit. The operation amplifier includes a non-reverse input terminal, a reverse input terminal and an output terminal coupled to the reverse input terminal for outputting an output voltage. The reference voltage generator is coupled to the non-reverse input terminal. The loading is coupled to the output terminal. The current source provides a starting current. The switching device is coupled between the current source and the output terminal, and turned on by an accelerating charging signal to pass the starting current to the loading through the first output terminal. The pulse output device outputs the accelerating charging signal.

Abstract: An active matrix LED display driving circuit. The circuit comprises a first transistor having a drain, a source coupled to receive a data signal and a gate coupled to receive a scan signal and, a second transistor having a drain, a source coupled to receive the data signal and a gate coupled to receive the scan signal, a third transistor having a source, a drain coupled to the drain of the second transistor and a gate coupled to the drain of the first transistor, a fourth transistor having a drain coupled to receive a first voltage, and a gate coupled to receive the scan signal and a source coupled to the drain of the second transistor, a light emitting diode having an anode coupled to the source of the third transistor and a cathode coupled to receive a second voltage, and a capacitor coupled between the gate and source of the third transistor.

Abstract: A reference voltage providing circuit. The operation amplifier includes a non-reverse input terminal, a reverse input terminal and an output terminal coupled to the reverse input terminal for outputting an output voltage. The reference voltage generator is coupled to the non-reverse input terminal. The loading is coupled to the output terminal. The current source provides a starting current. The switching device is coupled between the current source and the output terminal, and turned on by an accelerating charging signal to pass the starting current to the loading through the first output terminal. The pulse output device outputs the accelerating charging signal.

Abstract: A fast start up oscillator. The fast start-up oscillator includes a power-on-reset detect circuit, a bandgap circuit, a voltage detect circuit, a RC-oscillator, and a count two circuit. The fast start-up oscillator is provided with a fast stabilized voltage source to ensure oscillation accurate and quickly such that the system is woken up.

Abstract: A voltage-averaged temperature compensation method at start-up. The method implements two pluralities of PMOS devices such that a respective voltage-averaged temperature compensation circuit produces a first temperature voltage and a second temperature voltage to compensate temperature effect and accordingly produces an output voltage having a damping waveform in lower region when activating the first plurality of PMOS devices and a desired waveform in upper region when activating the second plurality of PMOS devices. As such, the error reference or control due to a prior damping waveform is eliminated.

Abstract: A dual-slope analog-to-digital converter and a comparison circuit for the dual-slope analog-to-digital converter. The dual-slope analog-to-digital converter includes a buffer, an integrator coupled to the buffer and the comparison circuit. The comparison circuit includes a differential output comparator and a comparison unit. The differential output comparator is coupled to the integrator and produces a pair of differential signals to output. The comparison unit receives the differential signals and chooses a signal, whose voltage is from a first level to a second level, from the differential signals to produce an output signal.

Abstract: A resistor-capacitor oscillator for receiving a current source, comprising a first switch path and a second switch path that are symmetric and connected in parallel. The first switch path comprises a signal output terminal and a first voltage output terminal. The second switch path comprises a complementary signal output terminal and the second voltage output terminal. One of these two voltage output terminals is selected randomly and input to both the first comparator and the second comparator simultaneously. The first comparator further receives a {fraction (1/2 )} VBG voltage, and the second comparator further receives 2VBG voltage. The first comparator outputs to a PMOS transistor, and the second comparator outputs to an NMOS transistor. The PMOS transistor is in series with the NMOS transistor, and is jointly coupled in between the system power supply and the ground voltage. Moreover, a latch and an inverter are serially coupled to the location of the serial junction node of these two transistors.