Abstract: A method of detecting for activating a temporal noise shaping process in coding audio signals comprises the steps of receiving continuous audio signals; computing a perceptual entropy value of each audio signal; comparing the perceptual entropy value with a threshold according to a discriminative condition; and activating temporal noise shaping process when a corresponding result is set true.

Abstract: A method for digital encoding of an audio stream in which the psychoacoustic modeling bases its computations upon an MDCT for the intensity and a spectral flatness measurement that replaces the phase data for the unpredictability measurement. This dramatically reduces computational overhead while also providing an improvement in objectively measured quality of the encoder output. This also allows for determination of tonal attacks to compute masking effects.

Abstract: A complex memory chip is provided. The complex memory chip comprises a first pin, a second pin, a voltage generator, a flash memory, and a static random access memory (SRAM). The first pin is capable of transmitting a first voltage. The second pin is capable of transmitting a second voltage which is lower than the first voltage, so as to define a working voltage in association with the first voltage. The voltage generator generates a third voltage according to the first voltage, wherein the third voltage is greater than the first voltage. The flash memory and the SRAM operate under the working voltage. The flash memory erases data according to the third voltage.

Abstract: A method of operating a dynamic random access memory (DRAM) using a bit line and a bit line bar is disclosed. The DRAM stores data by using a charge storage device, which is coupled to the bit line via a switch device. A voltage drop occurs when the switch device is turned on. The method programs the charge storage device with a first voltage or a zero voltage in response to a power voltage reduction due to the voltage drop. For accessing the data, the bit line and the bit line bar are charged to the power voltage, the switch device is turned on and the data stored in the charge storage device is determined according to a voltage difference between the bit line and the bit line bar.

Abstract: A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.

Abstract: A method of operating a memory device including an array of cells formed in rows and columns that comprises providing a control signal, activating the control signal, the activated control signal including a first state and a second state, continuously performing access cycles in response to the first state of the activated control signal in one part of a period, and continuously performing refresh cycles in response to the second state of the activated control signal in another part of the period.

Abstract: A method of operating a dynamic random access memory (DRAM) using a bit line and a bit line bar is disclosed. The DRAM stores data by using a charge storage device, which is coupled to the bit line via a switch device. A voltage drop occurs when the switch device is turned on. The method programs the charge storage device with a first voltage or a zero voltage in response to a power voltage reduction due to the voltage drop. For accessing the data, the bit line and the bit line bar are charged to the power voltage, the switch device is turned on and the data stored in the charge storage device is determined according to a voltage difference between the bit line and the bit line bar.

Abstract: A method for operating a memory device that comprises periodically generating a refresh request signal for performing a refresh operation, providing an access request signal for performing an access operation, performing the refresh operation if the refresh request signal occurs prior to the access request signal, and performing the access operation if the access request signal occurs prior to the refresh request signal.

Abstract: A signal processing method for audio signal compensation that corrects the high frequency audio signals while displaying music being removed with the high frequency audio signals is disclosed. When music being deleted with high-frequency audio signal is displayed, the deleted high-frequency audio signals are compensated by this method. At first, a first audio signal is inputted. Then increase output speed of the received first audio signal for outputting and producing a second audio signal. Sample a high frequency audio signal from the second audio signal and use this high frequency audio signal in compensation of the first audio signal, then output the compensated audio signal. Thus the quality of audio signals is improved and audio enjoyment for audience is increased.

Abstract: A computer system and a method for playing encrypted multimedia data are proposed. The computer system has a first operating system that heavily consumes system resources and a second operating system that slightly consumes the system resources. Via a basic input/output system (BIOS), the computer system is booted with a second operating system. The second operating system uses a multimedia-receiving unit to receive remote encrypted multimedia data and store the data into a storage unit. The second operating system uses a decrypting unit to access at least one kind of the encrypted multimedia data stored in the storage unit and the register information corresponding to the encrypted multimedia data from a first operating system for decryption. After the decrypting operation is completed, a playback unit is used to access the multimedia data that has been decrypted for perform a playback operation.

Abstract: A method of operating a memory device including an array of cells formed in rows and columns that comprises providing a control signal, activating the control signal, the activated control signal including a first state and a second state, continuously performing access cycles in response to the first state of the activated control signal in one part of a period, and continuously performing refresh cycles in response to the second state of the activated control signal in another part of the period.

Abstract: A system and method of a DVD player for displaying multiple subtitles includes a loading platform for reading digital data of DVD storage media; an interface management platform of receiving end for transmitting a decoded message of a first subtitle set image to a comparison platform. The comparison platform is for checking whether control signal of the first subtitle set image from the loading platform exists in an accumulator register. If not, the digital data is analyzed and decoded through an analytic platform and a decoder platform according to an identifying code of data flow and the first subtitle set image control signal. Then a mixed digital video signal and a digital audio signal are outputted by an image construct platform and an output platform.

Abstract: A semiconductor memory with shielding effect is disclosed in the invention. The memory includes at least a plurality of word lines, one ground line control unit, and a plurality of memory units. Every memory unit includes a primary bit line, a ground line, a first equivalent switch, and a second equivalent switch. The primary bit line is enabled by a control signal. The ground line and the ground line control unit are electrically connected. The first equivalent switch is coupled to both the primary bit line and the ground line, and is controlled by the control signal of the previous memory unit. The second equivalent switch is coupled to both the primary bit line and the ground line of the next memory unit, and is controlled by the control signal of the next memory unit.

Abstract: A low power consumption oscillation circuit and a delay circuit thereof are disclosed. The circuit comprises an enable circuit, an oscillator delay circuit and a feedback control network. The enable circuit is adapted for receiving an enable signal and performing an initial oscillation. The enable circuit outputs an initial oscillation signal according to a feedback control signal. The oscillator delay circuit is coupled to the enable circuit and is adapted for alternately generating a high and a low level oscillation signals according to the initial oscillation signal. The feedback control network is coupled to the oscillator delay circuit and is adapted for integrating the high and the low level oscillation signals to generate a feedback control signal and outputting the feedback control signal to the enable the circuit for activating next oscillation.

Abstract: A semiconductor memory with shielding effect is disclosed in the invention. The memory includes at least a plurality of word lines, one ground line control unit, and a plurality of memory units. Every memory unit includes a primary bit line, a ground line, a first equivalent switch, and a second equivalent switch. The primary bit line is enabled by a control signal. The ground line and the ground line control unit are electrically connected. The first equivalent switch is coupled to both the primary bit line and the ground line, and is controlled by the control signal of the previous memory unit. The second equivalent switch is coupled to both the primary bit line and the ground line of the next memory unit, and is controlled by the control signal of the next memory unit.

Abstract: A method of digital coding transforms input audio signals into a sequence of frequency samples representing a spectral composition of the audio signals, and quantizes the sequence of frequency samples into quantized values according to a bit allocation process which uses a parameter predictor to evaluate quantization parameters by referring to a masking threshold. The quantized values are encoded into a number of bits of encoded data. An iterative rate control loop adjusts the quantization parameters and the quantization step size if the number of bits in the encoded data exceeds a prescribed number of bits available for the encoded data. The method may also cut off high frequency components of the input audio signals according to a cut-off frequency determined by the iterative rate control loop before quantizing the sequence of frequency samples.

Abstract: An integrated circuit with on-chip resources to support the testing of data stored on the integrated circuit includes logic to compute a check code using data, or a combination of data and addresses, of a particular data set stored on the device. The check code produced using the stored version of the data set is compared with a test code produced using a correct version of the data set, to indicate whether the correct data set was successfully stored on the device. An on-chip store holds the code produced using the correct version, and an on-chip comparator is used to produce a flag indicating the success or failure of the test. During manufacturing of the device, the memory tester simply tests the flag.

Abstract: The present invention provides a ROM having a plurality of memory cell blocks each composed of a main bit line, a ground bit line, and a plurality of memory cells for storing information, which comprises: a plurality of up select transistors for selecting a memory cell block connected to the main bit line from a plurality of the memory cell blocks; and a plurality of down select transistors for selecting a memory cell block connected to the ground line from a plurality of the memory cell blocks, said up select transistors and down select transistors being arranged alternately with the memory cell block in between, wherein the layout pattern of said up select transistors and down select transistors being rotated 90 degrees. Under this kind of new layout pattern, the main bit lines and the ground bit lines will not be affected by the performing of ion implantation process, therefore, the junction leakage current will not be increased.

Abstract: A unified architecture for implementing the modified cosine transforms of various cosine modulated filter banks in audio compression standards comprises a permutation module and a transform computing module. A modified cosine transform is computed by a pre-permutation followed by a discrete cosine transform and an inverse modified cosine transform is computed by a discrete cosine transform followed by a post-permutation. The discrete cosine transform computed in the unified architecture is selected from the group of type-II, type-III and type-IV cosine transforms. The computation of an N point discrete cosine transform is decomposed into a permutation-add stage, a sub-transform stage for computing two N/2 point discrete cosine transforms selected from the same group, and a combination stage. The architecture results in good regularity and general applicability as well as reduces complexity.