Patents by Inventor Wen Chin Chen

Wen Chin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220229477
    Abstract: A heat dissipation system of a portable electronic device is provided. The heat dissipation system includes a body and at least one fan. A heat source of the portable electronic device is disposed in the body. The fan is a centrifugal fan disposed in the body. The fan has at least one flow inlet, at least one flow outlet, and at least one spacing portion. The flow outlet faces toward the heat source, and the spacing portion surrounds the flow inlet and abuts against the body, so as to isolate the flow inlet and the heat source in two spaces independent of each other in the body.
    Type: Application
    Filed: January 11, 2022
    Publication date: July 21, 2022
    Applicant: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Kuang-Hua Lin, Chun-Chieh Wang, Shu-Hao Kuo
  • Publication number: 20220214395
    Abstract: A control method is provided and used to place a target object on a test platform in a cabin of a testing device, to sense the temperature of the target object by a temperature response structure, and then to receive temperature signals of the temperature response structure by a controller, where the controller can regulate the pressure inside the cabin to control the air pressure of the cabin, so that the target object can still maintain good heat dissipation under high power consumption.
    Type: Application
    Filed: February 8, 2021
    Publication date: July 7, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chao-Ming Tu, Chih-Ming Yang, Wen-Chin Liang, Cheng-Shao Chen, Yung-Ming Wang
  • Patent number: 11379703
    Abstract: An identification system using electronic paper includes an external operation device and a portable identification device, the external operation device includes an external communication module for providing external display information; the portable identification device includes a wireless communication module, an electronic paper module, a timer module and a housing. The wireless communication module is configured to receive the external display information, and the electronic paper module includes a processing unit and a display unit. The processing unit is configured to drive the display unit according to the external display information so that the display unit displays an image including identification information and subsidiary information. The wireless communication module, the electronic paper module and the timer module are disposed in the housing so that the image is seen from the housing.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: July 5, 2022
    Assignee: YourSaaS Co., Ltd.
    Inventor: Wen Chin Chen
  • Publication number: 20220209666
    Abstract: The present invention provides a voltage control method for controlling a power supply. The voltage control method comprises the following steps: obtaining a present output voltage value associated with a present gain value; obtaining a predetermined output voltage value associated with a predetermined duty ratio; calculating a target gain value, corresponding to the predetermined duty ratio, according to a gain value formula; performing a weight calculation on the present gain value and the target gain value for generating a buffer gain value; and setting an output voltage command according to the buffer gain value. Wherein the buffer gain value is between the present gain value and the target gain value.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 30, 2022
    Inventors: Szu-Chieh SU, Wei-Chin TSENG, Chih-Hsien WANG, His-Ping TSAI, Wen-Chih CHEN, Guei-Cheng HU
  • Publication number: 20220207316
    Abstract: An identification system using electronic paper includes an external operation device and a portable identification device, the external operation device includes an external communication module for providing external display information; the portable identification device includes a wireless communication module, an electronic paper module, a timer module and a housing. The wireless communication module is configured to receive the external display information, and the electronic paper module includes a processing unit and a display unit. The processing unit is configured to drive the display unit according to the external display information so that the display unit displays an image including identification information and subsidiary information. The wireless communication module, the electronic paper module and the timer module are disposed in the housing so that the image is seen from the housing.
    Type: Application
    Filed: May 10, 2021
    Publication date: June 30, 2022
    Inventor: Wen Chin Chen
  • Publication number: 20210210350
    Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.
    Type: Application
    Filed: March 18, 2021
    Publication date: July 8, 2021
    Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
  • Patent number: 10957540
    Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
  • Publication number: 20200126793
    Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
  • Patent number: 10522353
    Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
  • Publication number: 20190324409
    Abstract: A clock using bright dot display comprises spaced illuminating display units arranged for the graduation marks of the clock, a micro processing unit which causes the illuminating display units of corresponding graduation marks to illuminate according to the time calculated by a time base unit. Each of the illuminating display units includes a first illuminating state, a second illuminating state and a third illuminating state. The illuminating display unit is the “hour indicator mark” in its first illuminating state, the “minute indicator mark” in its second illuminating state, and both the “hour indicator mark” and “minute indicator mark” in its third illuminating state. A user may easily read the time by observing the on and off states of the illumination of the “hour indicator mark” and “minute indicator mark” as well as the illumination colors of the illuminating display units.
    Type: Application
    Filed: April 22, 2018
    Publication date: October 24, 2019
    Inventors: WEN-CHIN CHEN, KUEI-CHUAN HO
  • Publication number: 20180350601
    Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.
    Type: Application
    Filed: July 24, 2018
    Publication date: December 6, 2018
    Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
  • Patent number: 10147609
    Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
  • Publication number: 20180337432
    Abstract: A lithium ion secondary battery includes a positive electrode plate including a positive electrode material and a negative electrode plate including a negative electrode material. An isolation membrane and an electrolyte are also included. A Prussian Blue analogue additive is in at least one of the positive electrode plate, the negative electrode plate, and the electrolyte. When the additive is included, the additive respectively has a mass percentage of about 0.5% to about 5% of a total mass of the positive electrode material or of the negative electrode material, or of the electrolyte.
    Type: Application
    Filed: August 16, 2017
    Publication date: November 22, 2018
    Inventors: CHAN-HSIANG HSU, MING-SHU KUO, WEN-CHIN CHEN, PO-YEN CHEN, CHIN-LUNG CHIU, FENG-YUEN DAI
  • Publication number: 20180294508
    Abstract: A lithium ion battery diaphragm includes a film and a ceramic layer, the ceramic layer is formed on at least one surface of the film to form a structure in the shape of a grid on the at least one surface of the film. A method for manufacturing the lithium ion battery diaphragm is also provided.
    Type: Application
    Filed: June 23, 2017
    Publication date: October 11, 2018
    Inventors: HSIN-NI CHIANG, CHIA-LIN MA, MING-SHU KUO, PO-YEN CHEN, WEN-CHIN CHEN, CHAN-HSIANG HSU, BI-SHENG JANG, YU-HSUAN TANG, CHIN-LUNG CHIU, FENG-YUEN DAI
  • Publication number: 20180175196
    Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.
    Type: Application
    Filed: March 31, 2017
    Publication date: June 21, 2018
    Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
  • Publication number: 20180125582
    Abstract: This invention provides a corneal surgery risk evaluation method and system thereof. Utilizing a mechanical numerical model to evaluate stress differences before corneal surgery and after, and further providing a suggested surgical path and risk after surgery. The evaluation method, comprising: measuring Intraocular pressure (IOP); inputting geometric parameters and material parameters of multi-layer of corneal; constructing a first corneal numerical model; constructing a second corneal numerical model with at least one cutting path character; evaluating whether the cutting path character should be re-constructed or not.
    Type: Application
    Filed: November 8, 2017
    Publication date: May 10, 2018
    Inventors: Wen-Pin SHIH, Wen-Chin CHEN
  • Patent number: 9748555
    Abstract: A Ni—Mn composite oxalate powder is provided. The Ni—Mn composite oxalate powder includes a plurality of biwedge octahedron particles represented by the general formula: NiqMnxCoyMzC2O4.nH2O, wherein q+x+y+z=1, 0<q, x<1, 0?y<1, 0?z<0.15, 0?n?5, and M is at least one of Mg, Sr, Ba, Cd, Zn, Al, Ga, B, Zr, Ti, Ca, Ce, Y, Nb, Cr, Fe and V. The above powder may be further calcined with a lithium salt to form a lithium transition metal oxide powder for use as a positive electrode material in lithium ion-batteries.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: August 29, 2017
    Assignees: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, NATIONAL TAIWAN UNIVERSITY
    Inventors: Hung-Chun Wu, Yu-Ting Chen, Nae-Lih Wu, Wen-Chin Chen, Shih-Chieh Liao, Yih-Chyng Wu
  • Patent number: 9590244
    Abstract: The disclosure provides a Ni—Mn composite oxalate powder, including a plurality of biwedge octahedron particles represented by the general formula: NiqMnxCoyMzC2O4.nH2O, wherein q+x+y+z=1, 0<q, x<1, 0?y<1, 0?z<0.15, 0?n?5, and M is at least one of Mg, Sr, Ba, Cd, Zn, Al, Ga, B, Zr, Ti, Ca, Ce, Y, Nb, Cr, Fe and V. The above powder may be further calcined with a lithium salt to form a lithium transition metal oxide powder for use as a positive electrode material in lithium ion-batteries.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: March 7, 2017
    Assignees: Industrial Technology Research Institute, National Taiwan University
    Inventors: Hung-Chun Wu, Yu-Ting Chen, Nae-Lih Wu, Wen-Chin Chen, Shih-Chieh Liao, Yih-Chyng Wu
  • Publication number: 20160302311
    Abstract: The present disclosure relates, according to some embodiments, to a method of fabricating a flexible metal-clad laminate comprising forming a metal layer on a surface of a polyimide film, wherein the metal layer and the polyimide film are contacting each other and forming a laminate, and heating the laminate at a temperature of about 80° C. to about 140° C. until a weight loss of the laminate reaches about 1% or higher.
    Type: Application
    Filed: April 8, 2016
    Publication date: October 13, 2016
    Inventors: Chung-Yi Chen, Akihisa Hamazawa, Wen-Chin Chen, Chien-Feng Chiu, Shih-Cheng Fan
  • Patent number: 9187452
    Abstract: The present invention provides a method for preparing Nilotinib of the following structure: by direct condensation of an ester and an aniline promoted by trialkyl aluminum in an organic solvent.
    Type: Grant
    Filed: September 7, 2014
    Date of Patent: November 17, 2015
    Assignee: FORMOSA LABORATORIES, INC.
    Inventors: Jui-Te Hung, Wen-Chin Chen