Patents by Inventor Wen Chin Lin
Wen Chin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210035621Abstract: A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.Type: ApplicationFiled: March 2, 2020Publication date: February 4, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Chin Lin, Hung-Chang Yu
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Patent number: 10753917Abstract: A hydrogen sensing device includes a multi-layered structure member. The multi-layered structure member includes a stack of alternatingly disposed magnetic layers and non-ferromagnetic layers. One of the magnetic layers is a topmost layer of the multi-layered structure member. The topmost layer includes a palladium-based material to detect hydrogen.Type: GrantFiled: May 11, 2018Date of Patent: August 25, 2020Assignee: NATIONAL CHIAO TUNG UNIVERSITYInventors: Yuan-Chieh Tseng, Jaw-Yeu Liang, Yun-Chieh Pai, Yu-Jung Chou, Wen-Chin Lin, Chih-Huang Lai
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Patent number: 10734276Abstract: A planarization method is provided and includes the following steps. A substrate having a main surface is provided. A protruding structure is formed on the main surface. An insulating layer is formed conformally covering the main surface and the top surface and the sidewall of the protruding structure. A stop layer is formed on the insulating layer and at least covers the top surface of the protruding structure. A first dielectric layer is formed blanketly covering the substrate and the protruding structure and a chemical mechanical polishing process is then performed to remove a portion of the first dielectric layer until a portion of the stop layer is exposed thereby obtaining an upper surface. A second dielectric layer having a pre-determined thickness is formed covering the upper surface.Type: GrantFiled: January 4, 2018Date of Patent: August 4, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Po-Cheng Huang, Yu-Ting Li, Fu-Shou Tsai, Wen-Chin Lin, Chun-Liang Liu
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Patent number: 10276367Abstract: A method for improving wafer surface uniformity is disclosed. A wafer including a first region and a second region is provided. The first region and the second region have different pattern densities. A conductive layer is formed on the wafer. A buffer layer is then formed on the conductive layer. The buffer layer is polished until the conductive layer is exposed. A portion of the conductive layer and the remaining buffer layer are etched away.Type: GrantFiled: January 9, 2018Date of Patent: April 30, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Jen-Chieh Lin, Wen-Chin Lin, Yu-Ting Li
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Patent number: 10262869Abstract: A planarization method includes providing a substrate having a semiconductor structure formed thereon. A dielectric layer is formed on the substrate, and a mask layer is formed on the dielectric layer. A first chemical mechanical polishing process is performed to remove a portion of the mask layer thereby forming an opening directly over the semiconductor structure and exposing the dielectric layer. A first etching process is performed to anisotropically remove a portion of the dielectric layer from the opening. The mask layer is then removed and a second chemical mechanical polishing process is then performed.Type: GrantFiled: February 25, 2018Date of Patent: April 16, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Jen-Chieh Lin, Lee-Yuan Chen, Wen-Chin Lin, Chi-Lune Huang, Pi-Hung Chuang, Tai-Lin Chen, Sun-Hong Chen
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Patent number: 10249357Abstract: A semiconductor device includes a substrate having a memory region and a peripheral region defined thereon, wherein the peripheral region comprises at least one transistor, the memory region comprises a plurality of memory cells, each memory cell comprises at least one gate structure and a capacitor structure, a mask layer disposed on the capacitor structure in the memory region, and a dielectric layer disposed on the substrate within the peripheral region, wherein a top surface of the dielectric layer is aligned with a top surface of the mask layer.Type: GrantFiled: November 23, 2017Date of Patent: April 2, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Wen-Chin Lin, Jhih-Yuan Chen, Syue-Ren Wu, Meng-Hsun Wu
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Publication number: 20190043866Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.Type: ApplicationFiled: October 3, 2018Publication date: February 7, 2019Inventors: Yu-Ting Li, Jen-Chieh Lin, Wen-Chin Lin, Po-Cheng Huang, Fu-Shou Tsai
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Publication number: 20190035794Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.Type: ApplicationFiled: October 3, 2018Publication date: January 31, 2019Inventors: Yu-Ting Li, Jen-Chieh Lin, Wen-Chin Lin, Po-Cheng Huang, Fu-Shou Tsai
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Publication number: 20180328902Abstract: A hydrogen sensing device includes a multi-layered structure member. The multi-layered structure member includes a stack of alternatingly disposed magnetic layers and non-ferromagnetic layers. One of the magnetic layers is a topmost layer of the multi-layered structure member. The topmost layer includes a palladium-based material to detect hydrogen.Type: ApplicationFiled: May 11, 2018Publication date: November 15, 2018Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: Yuan-Chieh TSENG, Jaw-Yeu Liang, Yun-Chieh Pai, Yu-Jung Chou, Wen-Chin Lin, Chih-Huang Lai
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Patent number: 10128251Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.Type: GrantFiled: September 9, 2016Date of Patent: November 13, 2018Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yu-Ting Li, Jen-Chieh Lin, Wen-Chin Lin, Po-Cheng Huang, Fu-Shou Tsai
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Publication number: 20180277382Abstract: A planarization method includes providing a substrate having a semiconductor structure formed thereon. A dielectric layer is formed on the substrate, and a mask layer is formed on the dielectric layer. A first chemical mechanical polishing process is performed to remove a portion of the mask layer thereby forming an opening directly over the semiconductor structure and exposing the dielectric layer. A first etching process is performed to anisotropically remove a portion of the dielectric layer from the opening. The mask layer is then removed and a second chemical mechanical polishing process is then performed.Type: ApplicationFiled: February 25, 2018Publication date: September 27, 2018Inventors: Jen-Chieh Lin, Lee-Yuan Chen, Wen-Chin Lin, Chi-Lune Huang, Pi-Hung Chuang, Tai-Lin Chen, Sun-Hong Chen
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Publication number: 20180197749Abstract: A planarization method is provided and includes the following steps. A substrate having a main surface is provided. A protruding structure is formed on the main surface. An insulating layer is formed conformally covering the main surface and the top surface and the sidewall of the protruding structure. A stop layer is formed on the insulating layer and at least covers the top surface of the protruding structure. A first dielectric layer is formed blanketly covering the substrate and the protruding structure and a chemical mechanical polishing process is then performed to remove a portion of the first dielectric layer until a portion of the stop layer is exposed thereby obtaining an upper surface. A second dielectric layer having a pre-determined thickness is formed covering the upper surface.Type: ApplicationFiled: January 4, 2018Publication date: July 12, 2018Inventors: Po-Cheng Huang, Yu-Ting Li, Fu-Shou Tsai, Wen-Chin Lin, Chun-Liang Liu
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Patent number: 9972498Abstract: A method of fabricating a gate cap layer includes providing a substrate with an interlayer dielectric disposed thereon, wherein a recess is disposed in the interlayer dielectric and a metal gate fills in a lower portion of the recess. Later, a cap material layer is formed to cover the interlayer dielectric and fill in an upper portion of the recess. After that, a first sacrifice layer and a second sacrifice layer are formed in sequence to cover the cap material layer. The first sacrifice layer has a composition different from a composition of the cap material layer. The second sacrifice layer has a composition the same as the composition of the cap material layer. Next, a chemical mechanical polishing process is preformed to remove the second sacrifice layer, the first sacrifice layer and the cap material layer above a top surface of the interlayer dielectric.Type: GrantFiled: March 27, 2016Date of Patent: May 15, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Shou Tsai, Yu-Ting Li, Chih-Hsun Lin, Li-Chieh Hsu, Yi-Liang Liu, Po-Cheng Huang, Kun-Ju Li, Wen-Chin Lin
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Publication number: 20180076205Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.Type: ApplicationFiled: September 9, 2016Publication date: March 15, 2018Inventors: Yu-Ting Li, Jen-Chieh Lin, Wen-Chin Lin, Po-Cheng Huang, Fu-Shou Tsai
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Publication number: 20180033636Abstract: A method of fabricating a semiconductor structure is provided. A substrate surface is provided and a first layer is disposed on the substrate surface. A second layer covering the first layer is formed wherein the materials of the first layer and the second layer are different. A first polishing operation is performed on the second layer until a first polished surface exposing a portion of the first layer is obtained. A second polishing operation is performed on the first polished surface to obtain a second polished surface wherein an upper portion of the exposed portion of the first layer is removed. None of the substrate is exposed from the first polished surface and the second polished surface.Type: ApplicationFiled: July 27, 2016Publication date: February 1, 2018Inventors: Li-Chieh Hsu, Fu-Shou Tsai, Yu-Ting Li, Po-Cheng Huang, Yi-Liang Liu, Wen-Chin Lin, Chun-Yi Wang, Chun-Yuan Wu
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Publication number: 20170162402Abstract: A method of manufacturing a semiconductor structure is provided. First, a preliminary structure is provided. The preliminary structure has a first region and a second region, and the preliminary structure comprises a plurality of features in the first region. Then, a first polish stop layer is formed on the preliminary structure. The first polish stop layer comprises a concave portion in the second region, and the concave portion defines an opening. A first overlying layer is formed on the first polish stop layer. Thereafter, a second polish stop layer is formed on the first overlying layer. The second polish stop layer has a graduated change in composition. The second polish stop layer comprises a concave portion at least partially formed in the opening. A second overlying layer is formed on the second polish stop layer.Type: ApplicationFiled: December 7, 2015Publication date: June 8, 2017Inventors: Fu-Shou Tsai, Yu-Ting Li, Li-Chieh Hsu, Kun-Ju Li, Chih-Hsun Lin, Po-Cheng Huang, Yi-Liang Liu, Wen-Chin Lin
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Publication number: 20170162396Abstract: A method of fabricating a gate cap layer includes providing a substrate with an interlayer dielectric disposed thereon, wherein a recess is disposed in the interlayer dielectric and a metal gate fills in a lower portion of the recess. Later, a cap material layer is formed to cover the interlayer dielectric and fill in an upper portion of the recess. After that, a first sacrifice layer and a second sacrifice layer are formed in sequence to cover the cap material layer. The first sacrifice layer has a composition different from a composition of the cap material layer. The second sacrifice layer has a composition the same as the composition of the cap material layer. Next, a chemical mechanical polishing process is preformed to remove the second sacrifice layer, the first sacrifice layer and the cap material layer above a top surface of the interlayer dielectric.Type: ApplicationFiled: March 27, 2016Publication date: June 8, 2017Inventors: Fu-Shou Tsai, Yu-Ting Li, Chih-Hsun Lin, Li-Chieh Hsu, Yi-Liang Liu, Po-Cheng Huang, Kun-Ju Li, Wen-Chin Lin
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Patent number: 9673053Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.Type: GrantFiled: November 20, 2014Date of Patent: June 6, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Rung-Yuan Lee, Yu-Ting Li, Jing-Yin Jhang, Chen-Yi Weng, Jia-Feng Fang, Yi-Wei Chen, Wei-Jen Wu, Po-Cheng Huang, Fu-Shou Tsai, Kun-Ju Li, Wen-Chin Lin, Chih-Chien Liu, Chih-Hsun Lin, Chun-Yuan Wu
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Publication number: 20160351674Abstract: A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface. A semiconductor structure formed by said semiconductor process is also provided.Type: ApplicationFiled: August 9, 2016Publication date: December 1, 2016Inventors: Kun-Ju Li, Po-Cheng Huang, Yu-Ting Li, Jen-Chieh Lin, Chih-Hsun Lin, Tzu-Hsiang Hung, Wu-Sian Sie, I-Lun Hung, Wen-Chin Lin, Chun-Tsen Lu
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Patent number: 9502303Abstract: A method for manufacturing a semiconductor device is provided. A substrate with an insulation formed thereon is provided, wherein the insulation has plural trenches, and the adjacent trenches are spaced apart from each other. A barrier layer is formed on an upper surface of the insulation and in sidewalls of the trenches, and the barrier layer comprises overhung portions corresponding to the trenches. A seed layer is formed on the barrier layer. Then, an upper portion of the seed layer formed on an upper surface of the barrier layer is removed. An upper portion of the barrier layer is removed for exposing the upper surface of the insulation. Afterwards, the conductors are deposited along the seed layer for filling up the trenches, wherein the top surfaces of the conductors are substantially aligned with the upper surface of the insulation.Type: GrantFiled: April 9, 2015Date of Patent: November 22, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kun-Ju Li, Kuo-Chin Hung, Po-Cheng Huang, Yu-Ting Li, Wu-Sian Sie, Chun-Tsen Lu, Wen-Chin Lin, Fu-Shou Tsai