Abstract: The present disclosure provides a semiconductor package including a bottom package having a substrate, a radio-frequency (RF) die and a system-on-a-chip (SoC) die arranged on the substrate in a side-by-side manner, a molding compound covering the RF die and the SoC die, and an interposer over the molding compound. Connection elements and a column of signal interference shielding elements are disposed on the substrate. The connection elements surround the SoC die. The column of signal interference shielding elements is interposed between the RF die and the SoC die. A top package is mounted on the interposer.

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.

Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.

Abstract: A semiconductor package includes a bottom chip package having a first side and a second side opposing the first side. The bottom chip package comprises a first semiconductor chip and a second semiconductor chip arranged in a side-by-side manner on the second side. A top antenna package is mounted on the first side of the bottom chip package. The top antenna package comprises a radiative antenna element. A connector is disposed on the second side.

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure.

Abstract: An Antenna-in-Package (AiP) includes an interface layer having at least an antenna layer and an insulating layer disposed under the antenna layer. The antenna layer includes a first antenna region and a second antenna region spaced apart from the first antenna region. An integrated circuit die is disposed on the interface layer. The integrated circuit die is interposed between the first antenna region and the second antenna region. The first antenna region includes a first antenna element, a second antenna element extending along a first direction, and a feeding network electrically connecting the first antenna element and the second antenna element to the integrated circuit die. The feeding network, the first antenna element, and the second antenna element are coplanar. A plurality of solder balls is disposed on a surface of the interface layer.

Abstract: An Antenna-in-Package (AiP) includes an interface layer, an integrated circuit die disposed on the interface layer, a molding compound disposed on the interface layer and encapsulating the integrated circuit die, and a plurality of solder balls disposed on a bottom surface of the interface layer. The interface layer includes an antenna layer, and an insulating layer between the antenna layer and the ground reflector layer. The antenna layer includes a first antenna region and a second antenna region spaced apart from the first antenna region. The integrated circuit die is interposed between the first antenna region and the second antenna region. The first antenna region is disposed adjacent to a first edge of the integrated circuit die, and the second antenna region is disposed adjacent to a second edge of the integrated circuit die, which is opposite to the first edge.

Abstract: An over-the-air (OTA) wireless test system includes a container, a machine plate disposed on the container, a supporter disposed on the machine plate, a load board disposed on the supporter, a socket disposed on the load board, a device under test (DUT) installed in the socket, and a wave-guiding feature in the socket and the load board configured to pass and guide electromagnetic waves to and/or from an antenna structure of the DUT. The wave-guiding feature comprises a wave-guiding channel in the socket defined by a plurality of pogo pins surrounding the antenna structure of the DUT. The wave-guiding feature may further comprise a radiation passage in the load board defined by rows of via fence extending through an entire thickness of the load board.

Abstract: A Radio Frequency (RF) device may include a plurality of antennas and one or more conductive traces configured to trap a portion of energy transmitted from at least one of the plurality of antennas. The one or more conductive traces are sized and positioned such that undesired coupling between the plurality of antennas may be suppressed while maintaining performance parameters of at least one of the plurality of antennas. The plurality of antennas and the one or more conductive traces may be formed using a redistribution layer coupled to a chip embedded in a molding layer.

Abstract: The present disclosure provides a semiconductor package including a bottom package having a substrate, a radio-frequency (RF) die and a system-on-a-chip (SoC) die arranged on the substrate in a side-by-side manner, a molding compound covering the RF die and the SoC die, and an interposer over the molding compound. Connection elements and a column of signal interference shielding elements are disposed on the substrate. The connection elements surround the SoC die. The column of signal interference shielding elements is interposed between the RF die and the SoC die. A top package is mounted on the interposer.

Abstract: A semiconductor device includes a first layer structure, a first layer structure, a second layer structure and a passive electronic component. The second layer structure is disposed below the first layer structure and coupled to a ground. The conductive structure is coupled to the first layer structure. The conductive structure is installed vertically between the first layer structure and the second layer structure, and is coupled to a first pad of the second layer structure. The passive electronic component comprises a first terminal coupled to the first pad of the second layer structure and a second terminal coupled to a second pad of the second layer structure. The conductive structure and the passive electronic component are connected in series between the first layer structure and the ground to form a conductive path for conducting at least one electromagnetic interference signal to the ground.

Abstract: A semiconductor device includes a first layer structure, a first layer structure, a second layer structure and a passive electronic component. The second layer structure is disposed below the first layer structure and coupled to a ground. The conductive structure is coupled to the first layer structure. The conductive structure is installed vertically between the first layer structure and the second layer structure, and is coupled to a first pad of the second layer structure. The passive electronic component comprises a first terminal coupled to the first pad of the second layer structure and a second terminal coupled to a second pad of the second layer structure. The conductive structure and the passive electronic component are connected in series between the first layer structure and the ground to form a conductive path for conducting at least one electromagnetic interference signal to the ground.

Abstract: A microelectronic assembly includes a substrate and a first microelectronic component mounted on the substrate. The first microelectronic component includes a digital/analog IP block and a RF IP block. A shielding case is mounted on the substrate. The shielding case includes a plurality of sidewalls, one intermediate wall, and a lid. A thermal interface material (TIM) layer is situated between the lid and the first microelectronic component. A noise suppressing structure is interposed between the TIM layer and the first microelectronic component.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a package substrate. An integrated circuit (IC) die having a radio frequency (RF) circuit and a memory die are stacked over the package substrate. The memory die entirely covers a first surface portion of the package substrate to define a second surface portion of the package substrate exposed from the memory die, and the IC die partially covers the first surface portion and the second surface portion of the package substrate. The RF circuit includes a first sensitive device region corresponding to the second surface portion of the package substrate and a second sensitive device region corresponding to the first surface portion of the package substrate and offsetting a memory input/output (I/O) electrical path of the memory die, as viewed from a top-view perspective.

Abstract: An antenna structure includes a radiative antenna element disposed in a first conductive layer, a reflector ground plane disposed in a second conductive layer under the first conductive layer, a feeding network comprising a transmission line disposed in a third conductive layer under the second conductive layer, and at least one coupling element disposed in proximity to a feeding terminal that electrically couples one end of the transmission line to the radiative antenna element. The coupling element is capacitively coupled with the feeding terminal.

Abstract: A radar module includes a printed circuit board (PCB) and a semiconductor package mounted on the PCB. The semiconductor package comprises an integrated circuit die and a substrate for electrically connecting the integrated circuit die to the PCB. The substrate comprises an antenna layer integrated into the semiconductor package and electrically connected to the integrated circuit die for at least one of transmitting and receiving radar signals. A discrete pattern-shaping device is mounted on the PCB and is configured to shape a radiation pattern of the radar signals.

Abstract: An Antenna-in-Package (AiP) includes an interface layer, an integrated circuit die disposed on the interface layer, a molding compound disposed on the interface layer and encapsulating the integrated circuit die, and a plurality of solder balls disposed on a bottom surface of the interface layer. The interface layer includes an antenna layer, and an insulating layer between the antenna layer and the ground reflector layer. The antenna layer includes a first antenna region and a second antenna region spaced apart from the first antenna region. The integrated circuit die is interposed between the first antenna region and the second antenna region. The first antenna region is disposed adjacent to a first edge of the integrated circuit die, and the second antenna region is disposed adjacent to a second edge of the integrated circuit die, which is opposite to the first edge.

Abstract: A semiconductor package includes a substrate having thereon at least an antenna layer and a ground reflector layer under the antenna layer, a radio frequency (RF) die disposed on or in the substrate, an encapsulation layer disposed on the antenna layer of the substrate, and a frequency-selective surface (FSS) structure disposed on the encapsulation layer. The FSS structure is a two-dimensional periodic array of metal patterns of same shape and size. The FSS structure has highly reflective characteristic.

Abstract: An over-the-air (OTA) wireless test system includes a container, a machine plate disposed on the container, a supporter disposed on the machine plate, a load board disposed on the supporter, a socket disposed on the load board, a device under test (DUT) installed in the socket, and a wave-guiding feature in the socket and the load board configured to pass and guide electromagnetic waves to and/or from an antenna structure of the DUT. The wave-guiding feature comprises a wave-guiding channel in the socket defined by a plurality of pogo pins surrounding the antenna structure of the DUT. The wave-guiding feature may further comprise a radiation passage in the load board defined by rows of via fence extending through an entire thickness of the load board.

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure.