Patents by Inventor Wen-Chuan Chiang
Wen-Chuan Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240136420Abstract: A thin film transistor includes a substrate, a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer is located above the substrate. The gate insulating layer is located above the semiconductor layer. The gate is located above the gate insulating layer and overlapping with the semiconductor layer. The gate includes a first portion, a second portion and a third portion. The first portion is extending along the surface of the gate insulating layer and directly in contact with the gate insulating layer. The second portion is separated from the gate insulating layer. Taking the surface of the gate insulating layer as a reference, the top surface of the second portion is higher than the top surface of the first portion. The third portion connects the first portion to the second portion. The source and the drain are electrically connected to the semiconductor layer.Type: ApplicationFiled: December 1, 2022Publication date: April 25, 2024Applicant: AUO CorporationInventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
-
Publication number: 20240076422Abstract: A supported metallocene catalyst includes a carrier and a metallocene component. The carrier includes an inorganic oxide particle and an alkyl aluminoxane material. The inorganic oxide particle includes at least one inorganic oxide compound selected from the group consisting of an oxide of Group 3A and an oxide of Group 4A. The alkyl aluminoxane material includes an alkyl aluminoxane compound and an alkyl aluminum compound that is present in amount ranging from greater than 0.01 wt % to less than 14 wt % base on 100 wt % of the alkyl aluminoxane material. The metallocene component is supported on the carrier, and includes one of a metallocene compound containing a metal from Group 3B, a metallocene compound containing a metal from Group 4B, and a combination thereof. A method for preparing the supported metallocene catalyst and a method for preparing polyolefin using the supported metallocene catalyst are also disclosed.Type: ApplicationFiled: September 1, 2023Publication date: March 7, 2024Inventors: Jing-Cherng TSAI, Jen-Long WU, Wen-Hao KANG, Kuei-Pin LIN, Jing-Yu LEE, Jun-Ye HONG, Zih-Yu SHIH, Cheng-Hung CHIANG, Gang-Wei SHEN, Yu-Chuan SUNG, Chung-Hua WENG, Hsing-Ya CHEN
-
Patent number: 10847606Abstract: A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth.Type: GrantFiled: November 27, 2018Date of Patent: November 24, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chi Tu, Wen-Chuan Chiang, Chen-Jong Wang
-
Publication number: 20190096985Abstract: A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth.Type: ApplicationFiled: November 27, 2018Publication date: March 28, 2019Inventors: Kuo-Chi Tu, Wen-Chuan Chiang, Chen-Jong Wang
-
Patent number: 10157976Abstract: A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth.Type: GrantFiled: January 23, 2017Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chi Tu, Wen-Chuan Chiang, Chen-Jong Wang
-
Patent number: 9793212Abstract: An embodiment semiconductor device includes a first conductive feature in a dielectric layer and a second conductive feature over the dielectric layer and electrically connected to the first conductive feature. The second conductive feature includes a dual damascene structure and further includes a top portion within both a line portion and a via portion of the second conductive feature and a bottom portion in the via portion of the second conductive feature. The bottom portion comprises a different conductive material than the top portion, and a thickness of the bottom portion is at least about twenty percent of a total thickness of the via portion of the second conductive feature.Type: GrantFiled: April 16, 2015Date of Patent: October 17, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chun Huang, Chih-Hsiang Yao, Jye-Yen Cheng, Wen-Chuan Chiang, Ying-Wen Huang
-
Patent number: 9728597Abstract: A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a bottom electrode layer over a substrate and forming a first passivation layer over the bottom electrode layer by a first atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a dielectric layer over the first passivation layer by a second atomic layer deposition process and forming a second passivation layer over the dielectric layer by a third atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a top electrode layer over the second passivation layer.Type: GrantFiled: July 15, 2015Date of Patent: August 8, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsing-Lien Lin, Chia-Shiung Tsai, Cheng-Yuan Tsai, Huey-Chi Chu, Hai-Dang Trinh, Wen-Chuan Chiang, Wei-Min Tseng
-
Publication number: 20170133452Abstract: A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth.Type: ApplicationFiled: January 23, 2017Publication date: May 11, 2017Inventors: Kuo-Chi Tu, Wen-Chuan Chiang, Chen-Jong Wang
-
Patent number: 9614025Abstract: A method of fabricating a semiconductor device comprises forming a first etch stop layer over a first dielectric layer. The method also comprises forming a first opening in the first etch stop layer and the first dielectric layer. The method further comprises filling the first opening with a conductive material. The method additionally comprises forming a second etch stop layer and a second dielectric layer over the first etch stop layer. The method further comprises forming a second opening to expose the conductive material. The method additionally comprises forming a capacitor in the second opening and in contact with the conductive material.Type: GrantFiled: February 19, 2016Date of Patent: April 4, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Yang Pai, Kuo-Chi Tu, Wen-Chuan Chiang, Chung-Yen Chou
-
Patent number: 9553095Abstract: A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth.Type: GrantFiled: December 11, 2013Date of Patent: January 24, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chi Tu, Wen-Chuan Chiang, Chen-Jong Wang
-
Publication number: 20160307793Abstract: An embodiment semiconductor device includes a first conductive feature in a dielectric layer and a second conductive feature over the dielectric layer and electrically connected to the first conductive feature. The second conductive feature includes a dual damascene structure and further includes a top portion within both a line portion and a via portion of the second conductive feature and a bottom portion in the via portion of the second conductive feature. The bottom portion comprises a different conductive material than the top portion, and a thickness of the bottom portion is at least about twenty percent of a total thickness of the via portion of the second conductive feature.Type: ApplicationFiled: April 16, 2015Publication date: October 20, 2016Inventors: Yi-Chun Huang, Chih-Hsiang Yao, Jye-Yen Cheng, Wen-Chuan Chiang, Ying-Wen Huang
-
Patent number: 9425247Abstract: A metal insulator metal (MIM) capacitor includes a top electrode, a first via contacting a first surface of the top electrode, a bottom electrode, a second via contacting a second surface of the bottom electrode, and an insulator between the top electrode and the bottom electrode. One of the top and the bottom electrodes includes a first part and a second part. The first part has a first edge and a second edge opposing the first edge. The second part shares the second edge with the first part. At least a portion of the first edge contacts the respective via, and a first one of the first and the second edges is longer than a second one of the first and the second edges.Type: GrantFiled: November 2, 2015Date of Patent: August 23, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Jong Wang, Huey-Chi Chu, Kuo-Ji Chen, Ming-Hsiang Song, Wen-Chuan Chiang
-
Patent number: 9391016Abstract: The present disclosure relates to an integrated chip having a MIM (metal-insulator-metal) capacitor and an associated method of formation. In some embodiments, the integrated chip has a MIM capacitor disposed within a capacitor inter-level dielectric (ILD) layer. An under-metal layer is disposed below the capacitor ILD layer and includes one or more metal structures located under the MIM capacitor. A plurality of vias vertically extend through the capacitor ILD layer and the MIM capacitor. The plurality of vias provide for an electrical connection to the MIM capacitor and to the under-metal layer. By using the plurality of vias to provide for vertical connections to the MIM capacitor and to the under-metal layer, the integrated chip does not use vias that are specifically designated for the MIM capacitor, thereby decreasing the complexity of the integrated chip fabrication.Type: GrantFiled: April 10, 2014Date of Patent: July 12, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Guo Shen, Wei-Min Tseng, Chien-Chung Wang, Huey-Chi Chu, Wen-Chuan Chiang
-
Publication number: 20160172435Abstract: A method of fabricating a semiconductor device comprises forming a first etch stop layer over a first dielectric layer. The method also comprises forming a first opening in the first etch stop layer and the first dielectric layer. The method further comprises filling the first opening with a conductive material. The method additionally comprises forming a second etch stop layer and a second dielectric layer over the first etch stop layer. The method further comprises forming a second opening to expose the conductive material. The method additionally comprises forming a capacitor in the second opening and in contact with the conductive material.Type: ApplicationFiled: February 19, 2016Publication date: June 16, 2016Inventors: Chih-Yang Pai, Kuo-Chi Tu, Wen-Chuan Chiang, Chung-Yen Chou
-
Patent number: 9368392Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor, and an associated method of formation. In some embodiments, the MIM capacitor includes a first electrode having a capacitor bottom metal layer disposed over a dielectric buffer layer located over an under-metal layer. A capacitor dielectric layer is disposed onto and in direct contact with the capacitor bottom metal layer. A second electrode having a top capacitor metal layer is disposed onto and in direct contact with the capacitor dielectric layer. A capacitor inter-level dielectric (ILD) layer is disposed over the top capacitor metal layer, and a substantially planar etch stop layer disposed over the capacitor ILD layer. The capacitor's simple stack provides for a small step size that prevents topography related issues, while the dielectric buffer layer removes design restrictions on the lower metal layer.Type: GrantFiled: April 10, 2014Date of Patent: June 14, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Min Tseng, Shih-Guo Shen, Chien-Chung Wang, Huey-Chi Chu, Wen-Chuan Chiang
-
Publication number: 20160163781Abstract: A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a bottom electrode layer over a substrate and forming a first passivation layer over the bottom electrode layer by a first atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a dielectric layer over the first passivation layer by a second atomic layer deposition process and forming a second passivation layer over the dielectric layer by a third atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a top electrode layer over the second passivation layer.Type: ApplicationFiled: July 15, 2015Publication date: June 9, 2016Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Hsing-Lien LIN, Chia-Shiung TSAI, Cheng-Yuan TSAI, Huey-Chi CHU, Hai-Dang TRINH, Wen-Chuan CHIANG, Wei-Min TSENG
-
Publication number: 20160071920Abstract: A metal insulator metal (MIM) capacitor includes a top electrode, a first via contacting a first surface of the top electrode, a bottom electrode, a second via contacting a second surface of the bottom electrode, and an insulator between the top electrode and the bottom electrode. One of the top and the bottom electrodes includes a first part and a second part. The first part has a first edge and a second edge opposing the first edge. The second part shares the second edge with the first part. At least a portion of the first edge contacts the respective via, and a first one of the first and the second edges is longer than a second one of the first and the second edges.Type: ApplicationFiled: November 2, 2015Publication date: March 10, 2016Inventors: Chen-Jong Wang, Huey-Chi Chu, Kuo-Ji Chen, Ming-Hsiang Song, Wen-Chuan Chiang
-
Patent number: 9269760Abstract: A method of fabricating a semiconductor device comprises forming a first etch stop layer over a first dielectric layer. The method also comprises forming a first trench in the first etch stop layer and the first dielectric layer. The method further comprises filling the first trench with a conductive material. The method additionally comprises forming a second etch stop layer over the first etch stop layer. The method also comprises forming a second dielectric layer over the second etch stop layer. The method further comprises forming a second trench to expose the conductive material. The second trench is formed having a depth less than a total thickness of the first etch stop layer, the second etch stop layer and the second dielectric layer. The method additionally comprises depositing a first metal layer over sidewalls of the second trench and in contact with the conductive material.Type: GrantFiled: January 27, 2015Date of Patent: February 23, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Yang Pai, Kuo-Chi Tu, Wen-Chuan Chiang, Chung-Yen Chou
-
Patent number: 9219110Abstract: The present disclosure relates to a MIM capacitor, and an associated method of formation. In some embodiments, the MIM capacitor has a first electrode having a bottom capacitor metal layer disposed over a semiconductor substrate. A second electrode having a middle capacitor metal layer overlies the bottom capacitor metal layer. A third electrode having a top capacitor metal layer has a stepped structure is laterally and vertically separated from the middle capacitor metal layer by a capacitor dielectric layer continuously extends from a first position between the bottom capacitor metal layer and the middle capacitor metal layer, to a second position between the middle capacitor metal layer and the top capacitor metal layer. The capacitor dielectric layer allows for the MIM capacitor to have a structure that improves fabrication of the capacitor.Type: GrantFiled: April 10, 2014Date of Patent: December 22, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Chung Wang, Wei-Min Tseng, Shih-Guo Shen, Huey-Chi Chu, Wen-Chuan Chiang
-
Patent number: 9178008Abstract: Methods and apparatus are disclosed for manufacturing metal-insulator-metal (MIM) capacitors. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, which has a bottle neck. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, in contact with a sidewall of a via. The sidewall contact or the bottle neck of the electrode may burn out to form a high impedance path when the leakage current exceeds a specification, while the sidewall contact or the bottle neck of the electrode has no impact for normal MIM operations. The MIM capacitors may be used as decoupling capacitors.Type: GrantFiled: August 10, 2012Date of Patent: November 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Ji Chen, Wen-Chuan Chiang, Huey-Chi Chu, Ming-Hsiang Song, Chen-Jong Wang