Abstract: A method and system is disclosed for examining mask pattern fidelity. A mask picture is generated from a first mask with a first OPC model applied to a mask design. The mask picture is converted into a mask based simulation file. A first simulation is conducted under a first set of predetermined lithography processing conditions using the converted simulation file to generate one or more files of a first set representing wafer photo resist profile thereof. The first OPC model is applied to the mask design in the database mask file. A second simulation is conducted under the first set of predetermined lithography processing conditions using the OPCed mask design to generate one or more files of a second set representing wafer photo resist profile thereof. The first and second sets of files are evaluated for inspecting mask fidelity.

Abstract: A method for patterning a substrate includes forming a material layer on the substrate; performing a first etching on the material layer to form a pattern; measuring the pattern of the material layer using an optical spectrum metrology tool; determining whether the measuring indicates that the etching step achieved a predefined result; and producing an etching recipe and performing a second etching of the material layer using the etching recipe if the predefined result was not achieved.

Abstract: A Light Emitting Diode (LED) package including a carrier, a package housing, an LED chip, and an electrostatic discharge protector (ESD protector) is provided. The package housing encapsulates a part of the carrier so as to provide a chip-accommodating space on the carrier. The LED chip disposed on the carrier and located in the chip-accommodating space is electrically connected to the carrier. The ESD protector disposed on the carrier and encapsulated by the package housing is electrically connected to the carrier. The LED package has excellent light-emitting intensity, since the light emitted from the LED chip is not absorbed by the ESD protector encapsulated by the package housing. Additionally, a fabricating method of the LED package is also provided.

Abstract: A patterning device for implementing a pattern on a substrate includes a main pattern feature and a sacrificial pattern feature. Both the main pattern feature and the sacrificial pattern feature are transferable to an overlying layer on the substrate. The sacrificial pattern feature is positioned a distance from the main pattern feature and is configured to have a dimension less than an etching bias of an etching process. The etching process is capable of transferring the main pattern feature to an underlying layer, such that the sacrificial pattern feature adjusts an etching behavior of the main pattern feature and is eliminated from the underlying layer.

Abstract: A system and method are disclosed for monitoring a dimensional change of a pattern for an object having a transparent layer exposed through the pattern and a non-transparent pattern laminated therewith. According to the method, a first beam is projected to the pattern. A second beam resulted from the first beam passing through the transparent layer exposed by the pattern, or from the first beam reflected from the non-transparent layer of the pattern, is detected. A value of a predetermined property from the second beam detected is obtained. A variation of the value is monitored for identifying the dimensional change of the pattern.

Abstract: A system for semiconductor wafer manufacturing, comprises a chamber process path for processing the wafer, and a device operable to remove particles from the wafer by electrostatic and electromagnetic methodologies wherein the device is installed in the chamber process path.

Abstract: A ribbon cartridge provides a tension mechanism to a ribbon inside the cartridge. By installing a frictional piece on one end of a ribbon-feeding bay of the ribbon cartridge, a feeding roller contacts the frictional piece and the frictional piece provides a frictional force for applying sufficient tension on the ribbon.

Abstract: A method of fabricating a photomask having improved critical dimension (CD) uniformity that meets or exceeds 90 nanometer technology requirements. The method includes the steps of: providing a transparent substrate covered with a layer of opaque material and a layer of photoresist; patterning the layer of photoresist to expose an area of the layer of opaque material that has a shape that follows a contour of a main pattern area to be defined by the layer of opaque material; removing the exposed area to define the layer of opaque material into the main pattern area and an area that surrounds the main pattern area; removing the patterned layer of photoresist; and removing the surrounding area of the layer of opaque material.

Abstract: An image processing system. An input/output device receives information for pixels in an image corresponding to an object, wherein the information specifies optical properties. A storage device stores the information. A processor determines an image of preliminary contour of the object based on the information. For pixels located on the preliminary contour are assigned as primary pixels, wherein anchor points determined by the location of the primary pixels, and the reference pixels determine modification vectors according to the information corresponding to the primary and reference pixels, and adjusts the positions of the anchor points according to the modification vectors. These processes are applied on every pixels or selected pixels located on the preliminary contour repeatedly to determine the final modified contour with sub-pixel accuracy.

Abstract: A hologram reticle and method of patterning a target. A layout pattern for an image to be transferred to a target is converted into a holographic representation of the image. A hologram reticle is manufactured that includes the holographic representation. The hologram reticle is then used to pattern the target. Three-dimensional patterns may be formed in a photoresist layer of the target in a single patterning step. These three-dimensional patterns may be filled to form three-dimensional structures. The holographic representation of the image may also be transferred to a top photoresist layer of a top surface imaging (TSI) semiconductor device, either directly or using the hologram reticle. The top photoresist layer may then be used to pattern an underlying photoresist layer with the image. The lower photoresist layer is used to pattern a material layer of the device.

Abstract: A method of fabricating a photomask having improved critical dimension (CD) uniformity that meets or exceeds 90 nanometer technology requirements. The method includes the steps of: providing a transparent substrate covered with a layer of opaque material and a layer of photoresist; patterning the layer of photoresist to expose an area of the layer of opaque material that has a shape that follows a contour of a main pattern area to be defined by the layer of opaque material; removing the exposed area to define the layer of opaque material into the main pattern area and an area that surrounds the main pattern area; removing the patterned layer of photoresist; and removing the surrounding area of the layer of opaque material.

Abstract: A multiple-exposure defect elimination process for semiconductor devices being fabricated on semiconductor wafers using photomask parts, including one mask part that is defective, is disclosed. A semiconductor wafer is exposed to a first mask part that is at least partially defective, and then is exposed to a second mask part corresponding to the first mask part but that is at least substantially free from defects or with defects at different locations. The mask parts may be on the same or different photomasks, and have the same layout for a semiconductor device that is being fabricated. Furthermore, the semiconductor wafer may be exposed to the second or other additional mask parts one or more additional times.

Abstract: A method and system is disclosed for examining mask pattern fidelity. First, a mask picture is generated from a first mask with a first OPC model applied to a mask design thereon. The mask picture is then converted into a mask based simulation file. A first simulation is conducted under a first set of predetermined lithography processing conditions using the converted simulation file to generate one or more files of a first set representing wafer photo resist profile thereof. On the other hand, a mask design in a database mask file is identified which was used for generating the first mask. The first OPC model is applied to the mask design in the database mask file. A second simulation is then conducted under the first set of predetermined lithography processing conditions using the OPCed mask design to generate one or more files of a second set representing wafer photo resist profile thereof. The first and second sets of files are then evaluated together for the purpose of inspecting mask fidelity.

Abstract: Electron beam (e-beam) shot linearity monitoring is disclosed. A pattern is written that has a predetermined size and a predetermined form in a predetermined position on a substrate, such as a semiconductor wafer, a reticle, or a photomask. The pattern writing fixes the e-beam shot size, as located along one or more critical dimensions of the pattern. The critical dimensions are then measured, where their variations reflect the e-beam shot size linearity. Thereafter, deficiencies in the e-beam shot size linearity can be compensated for, to allow for properly produced semiconductor patterns.

Abstract: Electron beam (e-beam) shot linearity monitoring is disclosed. A pattern is written that has a predetermined size and a predetermined form in a predetermined position on a substrate, such as a semiconductor wafer, a reticle, or a photomask. The pattern writing fixes the e-beam shot size, as located along one or more critical dimensions of the pattern. The critical dimensions are then measured, where their variations reflect the e-beam shot size linearity. Thereafter, deficiencies in the e-beam shot size linearity can be compensated for, to allow for properly produced semiconductor patterns.

Abstract: A method for forming a binary intensity mask (BIM) using two writing steps. The first writing step has a narrow writing area, preferably about 1 micron, and outlines the desired pattern. The second writing area partially overlaps the first writing area, preferably by less than half of the E-beam diameter used for writing. The second writing does not overlap the desired pattern. The chromium layer of the BIM is dry etched after the first writing, providing good edge definition and dimensional stability. The chromium layer of the BIM is wet etched following the second writing reducing mask defects.