Patents by Inventor Wen-Chun Liu
Wen-Chun Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9508634Abstract: A package structure includes a lead frame, a selective-electroplating epoxy compound, conductive vias and a patterned circuit layer. The lead frame includes a metal stud array having metal studs. The selective-electroplating epoxy compound covers the metal stud array. The selective-electroplating epoxy compound includes non-conductive metal complex. The conductive vias are directly embedded in the selective electroplating epoxy compound to be respectively connected to the metal studs and extended to a top surface of the selective-electroplating epoxy compound. Each of the conductive vias includes a lower segment connected to the corresponding metal stud and an upper segment connected to the lower segment and extended to the top surface, and a smallest diameter of the upper segment is greater than a largest diameter of the lower segment. The patterned circuit layer is directly disposed on the top surface and electrically connected to the conductive vias.Type: GrantFiled: April 20, 2016Date of Patent: November 29, 2016Assignee: IBIS Innotech Inc.Inventor: Wen-Chun Liu
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Patent number: 9451694Abstract: A package structure includes a selective-electroplating epoxy compound, a first patterned circuit layer, second patterned circuit layers, metal studs, contact pads and conductive vias. The selective-electroplating epoxy compound includes cavities, a first surface and a second surface. The cavities disposed on the first surface in array arrangement. The selective-electroplating epoxy compound is formed by combining non-conductive metal complex. The metal studs are disposed in the cavities respectively and protruded from the first surface. The first patterned circuit layer is directly disposed on the first surface. The selective-electroplating epoxy compound exposes a top surface of the patterned circuit layer. The top surface is lower than or coplanar with the first surface. The second patterned circuit layers are directly disposed on the second surface.Type: GrantFiled: March 19, 2015Date of Patent: September 20, 2016Assignee: IBIS Innotech Inc.Inventors: Chih-Kung Huang, Wei-Jen Lai, Wen-Chun Liu
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Publication number: 20160233152Abstract: A package structure includes a lead frame, a selective-electroplating epoxy compound, conductive vias and a patterned circuit layer. The lead frame includes a metal stud array having metal studs. The selective-electroplating epoxy compound covers the metal stud array. The selective-electroplating epoxy compound includes non-conductive metal complex. The conductive vias are directly embedded in the selective electroplating epoxy compound to be respectively connected to the metal studs and extended to a top surface of the selective-electroplating epoxy compound. Each of the conductive vias includes a lower segment connected to the corresponding metal stud and an upper segment connected to the lower segment and extended to the top surface, and a smallest diameter of the upper segment is greater than a largest diameter of the lower segment. The patterned circuit layer is directly disposed on the top surface and electrically connected to the conductive vias.Type: ApplicationFiled: April 20, 2016Publication date: August 11, 2016Inventor: Wen-Chun Liu
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Publication number: 20160067328Abstract: A recombinant neuraminidase based on amino acid sequence (SEQ ID NO: 1) of wild-type pH1N1-NA (A/Texas/05/2009) influenza virus is provided. The recombinant neuraminidase of the present invention has an ectodomain with an amino acid sequence essentially identical to SEQ ID NO: 1 and replaced at specific positions 149, 344, 365 and 366 residue(s) with corresponding amino acids of other influenza viruses. The recombinant neuraminidase may incur cross-protective immunity and be used as universal influenza vaccine.Type: ApplicationFiled: April 13, 2015Publication date: March 10, 2016Inventors: Suh-Chin WU, Wen-Chun LIU, Chia-Ying LIN
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Publication number: 20150373849Abstract: A package structure includes a selective-electroplating epoxy compound, a first patterned circuit layer, second patterned circuit layers, metal studs, contact pads and conductive vias. The selective-electroplating epoxy compound includes cavities, a first surface and a second surface. The cavities disposed on the first surface in array arrangement. The selective-electroplating epoxy compound is formed by combining non-conductive metal complex. The metal studs are disposed in the cavities respectively and protruded from the first surface. The first patterned circuit layer is directly disposed on the first surface. The selective-electroplating epoxy compound exposes a top surface of the patterned circuit layer. The top surface is lower than or coplanar with the first surface. The second patterned circuit layers are directly disposed on the second surface.Type: ApplicationFiled: March 19, 2015Publication date: December 24, 2015Inventors: Chih-Kung Huang, Wei-Jen Lai, Wen-Chun Liu
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Publication number: 20150364448Abstract: A package structure includes a chip, a selective-electroplating epoxy compound, a patterned circuit layer and a plurality of conductive vias. The chip includes a plurality of solder pads, an active surface and a back surface opposite to the active surface. The solder pads are disposed on the active surface. The selective-electroplating epoxy compound covers the chip and includes non-conductive metal complex. The patterned circuit layer is disposed directly on a surface of the selective-electroplating epoxy compound. The conductive vias are disposed directly at the selective-electroplating epoxy compound to electrically connect the solder pads and the patterned circuit layer.Type: ApplicationFiled: March 19, 2015Publication date: December 17, 2015Inventors: Chih-Kung Huang, Wei-Jen Lai, Wen-Chun Liu
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Publication number: 20150183833Abstract: The invention provides a deglycosylated hemagglutinin, wherein the glycosylation site(s) on the stem region is removed. The deglycosylated hemagglutinin may induce neutralizing antibody against influenza virus, and cross-reactive protection against different virus. The invention also provides a method for manufacturing deglycosylated hemagglutinin, comprising aligning two or more hemagglutinin stem sequences of influenza virus, identifying the high conserved N-glycosylation site, and removing the high conserved N-glycosylation site. Thus, the N-glycosylation site cannot be glycosyalted.Type: ApplicationFiled: March 7, 2014Publication date: July 2, 2015Applicant: National Tsing Hua UniversityInventors: Suh-Chin WU, Wen-Chun LIU, Yun-Ju HUANG
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Publication number: 20140221628Abstract: A DNA vaccine comprising hyperglycosylated mutant HA gene, which is derived from avian influenza virus, is provided. A DNA vaccine composition comprising: (a) the DNA vaccine; and (b) a booster is also provided. An influenza virus-like particle comprising adjuvant-fused M2 protein is further provided.Type: ApplicationFiled: April 8, 2014Publication date: August 7, 2014Applicant: NATIONAL TSING HUA UNIVERSITYInventors: Suh-Chin Wu, Wen-Chun Liu, Hung-Ju Wei
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Patent number: 6762118Abstract: An integrated circuit package structure having an array of metal pegs connected by printed circuit lines. The package includes a die pad having a die positioned above and an area array distribution of external metal pegs surrounding the die. The package also contains a plurality of internal metal pegs that surround the die. These internal pegs are electrically connected to the bonding pads on the die via conductive medium. The die pad, the die, the conductive medium and the internal pegs are all enclosed by an insulating material. The bottom side of the die pad is exposed while the external metal pegs are electrically connected to various internal metal pegs using printed circuit lines. Furthermore, an electroplate layer is also formed on the end face of each metal peg.Type: GrantFiled: February 25, 2002Date of Patent: July 13, 2004Assignee: Walsin Advanced Electronics Ltd.Inventors: Wen-Chun Liu, Chien-Hung Lai
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Publication number: 20030224542Abstract: A method for making multi-chip packages and single-chip packages simultaneously and structures thereof are provided. The method comprises the steps of chip-attaching, electrically connecting, encapsulating and electrically testing, all the step are executed on a package substrate with channel holes. The package substrate is selectively cut so as to form multi-chip packages and single-chip packages simultaneously. Each semiconductor package has a plurality of coplanar wiring substrates defined by the channel holes and selective cutting lines. A space between two adjacent wiring substrates is formed from corresponding channel hole and is filled with the isolating encapsulant so as to perform cushioning effect for reducing thermal stress and to improve the structure strength of the package assembly.Type: ApplicationFiled: May 29, 2002Publication date: December 4, 2003Applicant: Walsin Advanced Electronics LTDInventor: Wen-Chun Liu
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Patent number: 6486564Abstract: An improved heat dissipation module for BGA IC's is a thin metal module used for heat dissipation in an encapsulated IC device. It has an annular base with several supports extending from its inner rim upwards to support a top plate. At least one protruding annular ring is provided on the top surface of the top plate. This design can ensure the top plate and a mold match during the capsulation process, avoid the glue overflow problem, and increase its total dissipation area to facilitate heat dissipation.Type: GrantFiled: August 15, 2001Date of Patent: November 26, 2002Assignee: Walsin Advanced Electronics Ltd.Inventors: Wen-Chun Liu, Yi-Hsiang Pan, Kuo-Yuan Lee
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Publication number: 20020140113Abstract: A semiconductor die package has a lead frame, a die attached to the lead frame and an encapsulant enclosing the lead frame and the die. The distance between the top outside face of the encapsulant and the frame is substantially equal to the distance between the bottom outside face of the encapsulant and the die, and the distance between the top outside face of the encapsulant and the frame is substantially two and half times the distance between the bottom outside face of the encapsulant and the lead frame. Consequently, the different thickness of different encapsulant portions achieves an optimum balance during curing that effectively reduces the deformation of the encapsulant. In addition, the encapsulant can be completely formed by an injection process, and no crack will form in the encapsulant.Type: ApplicationFiled: March 27, 2001Publication date: October 3, 2002Applicant: WALSIN ADVANCED ELECTRONICS LTD.Inventors: Wen-Chun Liu, Yung-Chao Jen, Ming-Feng Wu
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Patent number: 6459162Abstract: A semiconductor die package has a lead frame, a die attached to the lead frame and an encapsulant enclosing the lead frame and the die. The distance between the top outside face of the encapsulant and the frame is substantially equal to the distance between the bottom outside face of the encapsulant and the die, and the distance between the top outside face of the encapsulant and the frame is substantially two and half times the distance between the bottom outside face of the encapsulant and the lead frame. Consequently, the different thickness of different encapsulant portions achieves an optimum balance during curing that effectively reduces the deformation of the encapsulant. In addition, the encapsulant can be completely formed by an injection process, and no crack will form in the encapsulant.Type: GrantFiled: March 27, 2001Date of Patent: October 1, 2002Assignee: Walsin Advanced Electronics Ltd.Inventors: Wen-Chun Liu, Yung-Chao Jen, Ming-Feng Wu
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Publication number: 20020127976Abstract: An integral micro-speaker having bi-directional dual magnetic field loops is provided. In general, the integral micro-speaker is incorporated into a wireless communication device such as a wireless telephone or a mobile telephone. The integral micro-speaker serves as a receiver and a speaker in a wireless telephone. The integral micro-speaker may further incorporate a vibrator for producing an added vibration function to the wireless telephone. In other words, a receiver, a speaker and a vibrator may be combined together to form an integral component inside the wireless telephone.Type: ApplicationFiled: March 9, 2001Publication date: September 12, 2002Inventor: Wen-Chun Liu
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Publication number: 20020089053Abstract: An integrated circuit package structure having an array of metal pegs connected by printed circuit lines. The package includes a die pad having a die positioned above and an area array distribution of external metal pegs surrounding the die. The package also contains a plurality of internal metal pegs that surround the die. These internal pegs are electrically connected to the bonding pads on the die via conductive medium. The die pad, the die, the conductive medium and the internal pegs are all enclosed by an insulating material. The bottom side of the die pad is exposed while the external metal pegs are electrically connected to various internal metal pegs using printed circuit lines. Furthermore, an electroplate layer is also formed on the end face of each metal peg.Type: ApplicationFiled: February 25, 2002Publication date: July 11, 2002Inventors: Wen-Chun Liu, Chien-Hung Lai
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Patent number: 6380062Abstract: A method for forming ball grid array package. The ball grid array package has internal trace lines and exposed metal pegs. A metal substrate is provided. Electroplated layers are formed over metal peg regions and a die pad region on the surface of the metal substrate. A layer of substrate material at the top surface of the metal substrate is removed so that thickness of the metal substrate is reduced. Hence, trace lines, die pad and internal metal pegs are formed. A die is attached to the die pad and electrical connections from the die to the internal metal pegs are made. A molding process is carried out to enclose the die, the die pad and the internal metal pegs on one side of the metal substrate with plastic material. The lower surface of the metal substrate is etched to form external metal pegs while exposing the mold material and the bottom surface of the die pad. The internal metal pegs and the external metal pegs are interconnected via the trace lines.Type: GrantFiled: March 9, 2001Date of Patent: April 30, 2002Assignee: Walsin Advanced Electronics Ltd.Inventor: Wen-Chun Liu
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Publication number: 20020020926Abstract: An improved heat dissipation module for BGA IC's is a thin metal module used for heat dissipation in an encapsulated IC device. It has an annular base with several supports extending from its inner rim upwards to support a top plate. At least one protruding annular ring is provided on the top surface of the top plate. This design can ensure the the top plate and a mold match during the capsulation process, avoid the glue overflow problem, and increase its total dissipation area to facilitate heat dissipation.Type: ApplicationFiled: August 15, 2001Publication date: February 21, 2002Inventors: Wen-Chun Liu, Yi-Hsiang Pan, Kuo-Yuan Lee
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Patent number: 6278182Abstract: A semiconductor package containing a silicon chip, a lead frame, a plurality of conductive wires, a heat sink and some packaging material. Both the silicon chip and the heat sink are mounted on the lead frame, and the silicon chip is located between the heat sink and the lead frame. The silicon chip is electrically connected to some contact points on the lead frame by a plurality of conductive wires, and the space between the heat sink and the lead frame is filled with packaging material. The heat sink has a narrow pinhole gate and a plurality of conical positioning holes. The pinhole gate is formed in the middle of the heat sink so that packaging material can enter the mold cavity in the middle through the roof of the package. Both the pinhole gate and the positioning holes are filled with packaging material.Type: GrantFiled: August 12, 1999Date of Patent: August 21, 2001Assignee: Walsin Advanced Electronics Ltd.Inventors: Wen-Chun Liu, Chien-Hung Lai
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Patent number: 6262475Abstract: The addition of a heat slug to a lead frame establishes a heat conduction path from a silicon chip on the lead frame to the heat slug. Hence, when a semiconductor package that encloses the lead frame and the silicon chip is formed, heat produced by the silicon chip can still be channeled away through the radiating surface of the heat slug. Furthermore, the heat slug can be bent over to cover burrs outside the package.Type: GrantFiled: February 16, 1999Date of Patent: July 17, 2001Assignees: Walsin Advanced Electronics Ltd., Sitron Precision Co., Ltd.Inventors: Wen-Chun Liu, Chih-Kung Huang
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Patent number: 6204553Abstract: A lead frame for a semiconductor package. The lead frame includes a die pad and a plurality of leads. One surface of the die pad supports a silicon chip while the other surface has a plurality of annular grooves all having the same geometric center. The inner lead portion of the leads surrounds the die pad, but the die pad and the leads are on different planar surfaces.Type: GrantFiled: August 10, 1999Date of Patent: March 20, 2001Assignee: Walsin Advanced Electronics Ltd.Inventors: Wen-Chun Liu, Hui-Ping Liu, Jung-Jie Liou, Yi-Hsiang Pan, Sheng-Tung Tsai