Abstract: Disclosed are a magnetic core structure and a magnetic component. The magnetic core structure includes N winding columns and two cover plates, and N is a positive integer, wherein each winding column is provided with a first hollow channel, the two cover plates are disposed at two ends of each winding column, each cover plate is provided with N first through holes, the N winding columns are in a one-to-one correspondence with the N first through holes of each cover plate, and the first hollow channel of each winding column is communicated with the first through holes located on two sides thereof and corresponding thereto. Therefore, the channels for air flow can be added, so that the heat dissipation efficiency is improved when the magnetic core structure is applied to the magnetic component.

Abstract: An optical structure is provided. The optical structure includes a substrate, a light-emitting element, a glue layer, and a light-adjusting element. The light-emitting element is disposed on the substrate. The glue layer covers the light-emitting element. The light-adjusting element is disposed on the glue layer. Moreover, the refractive index of the glue layer is different from the refractive index of the light-adjusting element.

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

Abstract: In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.

Abstract: A glass composition includes, based on 100 wt % of the glass composition, silicon dioxide present in an amount ranging from 45 wt % to 61 wt %, aluminum oxide present in an amount (A) ranging from 15 wt % to 22 wt %, calcium oxide present in an amount (C) ranging from 0.1 wt % to 6 wt %, magnesium oxide present in an amount (M) of greater than 0 wt % and lower than 2 wt %, zinc oxide present in an amount of greater than 0 wt % and lower than 8 wt %, copper oxide present in an amount of greater than 0 wt % and lower than 7 wt %, and boron oxide present in an amount of greater than 6 wt % and lower than 18 wt %. A glass fiber including the glass composition, and an electronic product including the glass fiber are also provided.

Abstract: A light-emitting device array includes a first light-emitting device, a second light-emitting device, and a third light-emitting device. A first beam shaping structure of the first light-emitting device is configured to convert light emitted by a first light-emitting structure of first light-emitting device into first structured light. A second beam shaping structure of the second light-emitting device is configured to convert light emitted by a second light-emitting structure of second light-emitting device into second structured light. Speckle patterns and spatial distributions of the first structured light and the second structured light on a projection plane are the same. A third beam shaping structure of the third light-emitting device is configured to convert light emitted by a third light-emitting structure of third light-emitting device into third structured light.

Abstract: A display module includes a light-emitting element, a molding layer, a metal contact, an insulating layer, and an array substrate. The light-emitting element has a first surface and a second surface opposite to each other. The light-emitting element has a lead disposed on the first surface. The molding layer laterally surrounds the light-emitting element and has a first surface and a second surface opposite to each other. The first surface of the molding layer is adjacent to the first surface of the light-emitting element. The first surface of the molding layer is a coarse surface. The metal contact covers the lead of the light-emitting element. The insulating layer covers the metal contact and the molding layer. The array substrate is disposed on the insulating layer and having a pad configured to be electrically connected to the metal contact.

Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes: providing an interposer having a front surface and a back surface, the interposer comprising a substrate, at least one routing region, and at least one non-routing region; forming at least one warpage-reducing trench in the at least one non-routing region, wherein the at least one warpage-reducing trench extends from the front surface of the interposer to a first depth, the first depth smaller than a thickness between the front surface and the back surface of the interposer; depositing a warpage-relief material in the at least one warpage-reducing trench; and bonding the group of IC dies to the front surface of the interposer.

Abstract: The present disclosure relates to methods, compositions, and kits for concentrating and purifying at least one target analyte from a clinical biological sample. In some embodiments, the methods involve one or more aqueous two-phase system (ATPS) compositions and at least one solid phase medium. Some embodiments provide a kit comprising one or more ATPS compositions, a binding buffer; and a solid phase medium. Other embodiments provide methods of treating cancers or infectious diseases in a patient in need thereof.

Abstract: In some implementations, one or more semiconductor processing tools may form a triple-stacked polysilicon structure on a substrate of a semiconductor device. The one or more semiconductor processing tools may form one or more polysilicon-based devices on the substrate of the semiconductor device, wherein the triple-stacked polysilicon structure has a first height that is greater than one or more second heights of the one or more polysilicon-based devices. The one or more semiconductor processing tools may perform a chemical-mechanical polishing (CMP) operation on the semiconductor device, wherein performing the CMP operation comprises using the triple-stacked polysilicon structure as a stop layer for the CMP operation.

Abstract: An image sensor structure and methods of forming the same are provided. An image sensor structure according to the present disclosure includes a semiconductor substrate including a photodiode, a transfer gate transistor disposed over the semiconductor substrate and having a first channel area, a first dielectric layer disposed over the semiconductor substrate, a semiconductor layer disposed over the first dielectric layer, a source follower transistor disposed over the semiconductor layer and having a second channel area, a row select transistor disposed over the semiconductor layer and having a third channel area, and a reset transistor disposed over the semiconductor layer and having a fourth channel area. The second channel area is greater than the first channel area, the third channel area or the fourth channel area.

Abstract: A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.

Abstract: Disclosed is a microfluidic detection device including a circuit substrate and a transparent substrate. The circuit substrate is provided with at least one first light-emitting device used to emit a detection beam, a photodetector used to receive the detection beam and send out a sensing signal, and a control circuit electrically connected to the first light-emitting device and the photodetector. The transparent substrate overlaps the circuit substrate and is provided with a microfluidic channel and a light guide structure. The light guide structure has a light incident surface disposed corresponding to the first light-emitting device and a light exiting surface disposed corresponding to the photodetector. The light guide structure extends from each of the light incident surface and the light exiting surface to the microfluidic channel and is adapted to transmit the detection beam into and out of the microfluidic channel.

Abstract: A speed reducer comprises a transmission shaft, an eccentric wheel, a first wheel assembly, a rotating wheel and a second wheel assembly. The first wheel assembly comprises a first wheel disc and at least one first roller. The at least one first roller is disposed on the inner wall of first wheel disc. The rotating wheel comprises a main body comprising an outer ring structure and a concave structure. The outer ring structure comprises at least one first tooth. The at least one first tooth is in contact with the corresponding first roller. At least one second roller is disposed within the concave structure. The second wheel assembly comprises a second wheel disc and at least one second tooth. The at least one second tooth is disposed on an outer periphery of the second wheel assembly. The at least one second tooth is in contact with the corresponding second roller.

Abstract: In some implementations, one or more semiconductor processing tools may form a first terminal of a semiconductor device by depositing a tunneling oxide layer on a first portion of a body of the semiconductor device, depositing a first volume of polysilicon-based material on the tunneling oxide layer, and depositing a first dielectric layer on an upper surface and a second dielectric layer on a side surface of the first volume of polysilicon-based material. The one or more semiconductor processing tools may form a second terminal of the semiconductor device by depositing a second volume of polysilicon-based material on a second portion of the body of the semiconductor device. A side surface of the second volume of polysilicon-based material is adjacent to the second dielectric layer.

Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

Abstract: A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.

Abstract: An E-paper display panel including an E-paper display layer, a first substrate, a pixel array layer, a common electrode layer, and a driving circuit is provided. The first substrate is disposed at a first side of the E-paper display layer. The pixel array substrate is disposed between the first substrate and the E-paper display layer and includes touch electrodes and driving pixels arranged in an array. Each driving pixel includes a first pixel electrode and a second pixel electrode. The touch electrodes, the first pixel electrode, and the second pixel electrode are overlapped with each other. The common electrode layer is disposed at a second side of the E-paper display layer. The first side is opposite to the second side. The driving circuit is in signal communication with the common electrode layer and the pixel array layer. The touch electrodes are individually in signal communication with the driving circuit.

Abstract: A process operating system includes a process control platform, a process operation platform and an endpoint task robot. The process control platform is configured to receive operation information, extract a task from the operation information using a semantic analysis method, and publish the task. The process operation platform is configured to receive the task and store the task in a task queue. After receiving the task, the process operating platform defines a processing flow based on the task, and sorts the order of the task in the task queue. The endpoint task robot is configured to automatically obtain the task from the process operation platform, executes the task according to the processing flow. It then writes the execution result into the log queue and transmits the execution result to the process control platform.

Abstract: A blood pressure measurement device includes a substrate, a protrusion portion, an image sensor, a first light source, a second light source, and a control and processing unit. The first light source projects a first light toward the base plat. A finger presses the protrusion portion, and the image sensor captures an image of a bright area. The processing unit calculates a number of light-receivable pixels of image sensor and compares with a number of pixels able to receive light of image sensor to obtain a ratio value, and determines whether the finger has enough pressure. The second light source projects a second light toward the substrate, penetrating the substrate and the finger skin to be reflected by a blood vessel. The image sensor captures an image of a changed volume of the blood vessel, and the control and processing unit calculates the systolic or diastolic pressure.