Abstract: An antenna element comprises one or more directors, a resonator, and a three dimensional ground assembly. Parts of the antenna element are arranged on three metal layers. A top layer has an unconnected metal bar which forms a beam director, a resonator and a top part of the ground assembly. The resonator is an integral piece substantially in the form of a loop connected to a feed line and a feed line terminal ending. The feed line terminal ending serves as the ground plane for the feed line as well as providing impedance matching from the external transceiver circuit to the resonator. The ground assembly includes a top layer ground connected to a plurality of metallized half cylindrical hole channels (or metallized via holes) which connect to a ground terminal in a bottom layer.

Abstract: A touch light-emitting module and a manufacturing method thereof are disclosed. The touch light-emitting module includes a printed circuit board and a touch-control conductor. The printed circuit board has a top surface on which a touch-control IC and a luminous unit that is electrically connected are disposed. The touch-control conductor includes a hollowed portion. The touch-control conductor is coated, on the bottom thereof, with a conductive material to combine with the top surface of the printed circuit board, so that the touch-control IC and the luminous unit are located in the hollowed portion. An encapsulation resin is then injected into a space between the printed circuit board and the hollowed portion to complete encapsulation. As such, the present invention offers a simplified structure to achieve an effect of minimization, and also simplifies the manufacturing process and reduces the working time to thereby enhance the yield.

Abstract: A semiconductor structure includes first and second inner seal rings each having a first section and a second section substantially perpendicular to the first section. The semiconductor structure further includes an outer seal ring. The outer seal ring has a third section, and a fourth section, and a fifth section. The semiconductor structure further includes dummy patterns substantially uniformly distributed in each of regions between the first inner seal ring and the outer seal ring and between the second inner seal ring and the outer seal ring.

Abstract: A method for fabricating a semiconductor device is provided. The method includes generating a redistribution layer (RDL) layout, wherein the RDL layout comprises a plurality of redistribution lines; determining a first dummy region in the RDL layout according to the redistribution lines; disposing a plurality of first dummy redistribution lines in the first dummy region; performing a first modification process to enlarge at least one of the first dummy redistribution lines; determining the enlarged one of the first dummy redistribution lines as a second dummy region in the RDL layout when an area of the enlarged one of the first dummy redistribution lines is greater than a threshold value; disposing a plurality of second dummy redistribution lines in the second dummy region; and patterning a metal layer according to the RDL layout after disposing the second dummy redistribution lines in the second dummy region.

Abstract: The present invention provides a surface light source projection device with improved zero-order diffraction, which includes a light exit module and a diffractive optical module. Wherein, the diffractive optical module has two micron diffractive layers, the micron diffractive layers include a plurality of microstructures, and the microstructures are provided with a first recess, and the first recess has a first depth and a first outer diameter. The outer diameter of the microstructures is between 5 times and 200 times the incident wavelength of the narrow half-wave width, and the first outer diameter of the first recess is between 0.3 and 0.7 times the outer diameter. As such, a surface light source projection device that can generate a diffraction pattern with uniform spot intensity and can illuminate for a long time is provided.

Abstract: An AC-to-DC power supply converts an input power source into an output power source, capable of having a single stage to achieve PFC and output regulation at the same time. The AC-to-DC power supply has an inductive device, a main switch, a backup circuit providing a backup power, and a power controller. The power controller controls the main switch and the backup circuit to generate a power transfer cycle with an input slot, an internal-burst slot, and a demagnetization time. During the input slot, the power controller turns ON the main switch, so the input power source supplies power to increase electromagnetic energy of the inductive device. During the internal-burst slot, the backup power supplies power to the inductive device. During the demagnetization time, the electromagnetic energy releases to supply power to the output power source or the backup power.

Abstract: A hypochlorous acid disinfectant and its production method. The disinfectant is prepared by weight in a total of 100% as chlorine powder (chlorine compounds including sodium hypochlorite or calcium hypochlorite) of 20 to 45%, adding sodium dihydrogen phosphate or citric acid, or ingredients or raw materials with acidic pH of 15 to 40% as a main ingredient, a desiccant of 15 to 20%, excipients of 3 to 8%. The method includes: stirring the chlorine powder with the desiccant; adding the sodium dihydrogen phosphate, the citric acid, or the ingredients or raw materials with acidic pH in order; and adding the excipient while stirring for 20 to 30 minutes until completely uniform to prepare the hypochlorous acid (powder) disinfectant. According to the method, a hypochlorous acid tablet disinfectant can be prepared.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an antenna zone and a routing zone. The routing zone is disposed on the antenna zone, where the antenna zone includes a first insulation layer and two or more second insulation layer and a thickness of the first insulation layer is different from that of the second insulation layer.

Abstract: An electrochromic device composed of a pattern forming layer, an optical coating layer, an electrochromic component, and an opaque white layer arranged is revealed. The pattern forming layer has at least one pattern-shaded hollow hole for exposure of the optical coating layer. The optical coating layer which includes at least two layers of high and low refractive index material stacked alternately is the main layer to render colors. When transmittance of the electrochromic component which generates color changes is lower than 50%, a difference in the transmittance at 500 nm, 600 nm, and 700 nm is no more than 10%. Under such colored state, the color of light reflected by the optical coating layer is enhanced. The opaque white layer is for a sharper color contrast of the reflected light. Thereby light reflected by the optical coating layer show colors different from those of the electrochromic component in bleached and colored states.

Abstract: Embodiments disclosed herein relate generally to methods for measuring a characteristic of a substrate. In an embodiment, the method includes scanning over the substrate with a scanning probe microscope, the substrate having fins thereon, the scanning obtaining images showing respective fin top regions of the fins, the scanning probe microscope interacting with respective portions of sidewalls of the fins by a scanning probe oscillated during the scanning, selecting images obtained at a predetermined depth below the fin top regions to obtain a line edge profile of the fins, by a processor-based system, analyzing the line edge profile of the fins using power spectral density (PSD) method to obtain spatial frequency data of the line edge profile of the fins, and by the processor-based system, calculating line edge roughness of the fins based on the spatial frequency data.

Abstract: A method for fabricating a transistor includes providing a substrate, having a gate region and a first trench in the substrate at a first side of the gate region; forming a first gate insulating layer, disposed on a first portion of the gate region, opposite to the first trench; forming a second gate insulating layer, disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer; forming a gate layer, disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench; forming a first doped region in the substrate at least under the first trench; and forming a second doped region in the substrate at a second side of the gate region.

Abstract: A semiconductor structure that includes two circuit regions; two inner seal rings, each of the two inner seal rings surrounding one of the two circuit regions; an outer seal ring surrounding the two inner seal rings, wherein each of the inner seal rings and the outer seal ring has a substantially rectangular periphery with four interior corner seal ring structures; four first redundant regions between the two inner seal rings and the outer seal ring, each of the four first redundant regions being a substantially trapezoidal shape; and first dummy patterns substantially uniformly distributed in the four first redundant regions.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over and passing through the insulating layer. The conductive pillar is formed in one piece, the conductive pillar is in direct contact with the first conductive line, and a first sidewall of the first conductive line extends across a second sidewall of the conductive pillar in a top view of the first conductive line and the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

Abstract: Light device control circuit includes signal processor; control circuit including control signal source and active switch, active switch having output end thereof electrically connected to control input side of the signal processor through control bus; data synchronization circuit including data signal source and another set of active switches, and the output end of the another set of active switches being electrically connected to data input side of signal processor through data bus, signal processor forming electrical connection with signal connection circuit by data output side to form signal and command synchronization between data input side and data output side; and warning light control IC connected to warning lights and forming electrical connection with data bus outside data output side, and transmitting data, clock pulse and ID information from data output side, so that the starter and the receivers select one of the flash modes to flash the light.

Abstract: The present invention provides a surface light source projection device, which includes a light emitting module and a diffractive optical module. Wherein, the diffractive optical module has two micron diffractive layers, the micron diffractive layers include a plurality of micron structures, and the shape of the micron structures is set to be cone, disc or any combination of the above. The micron structures have an outer diameter, and the outer diameter of the micron structures is between 5 times and 200 times of the Narrow half-wave width incident wavelength of the light beam output from the light emitting module. Thereby, the surface light source projection device capable of enduring heat accumulation generated after continuous irradiation of high-energy laser is provided to facilitate long-term irradiation and long-distance sensing.

Abstract: The present disclosure relates to an electronic load apparatus. An embodiment of the present disclosure includes an electronic load apparatus including: a measurement resistor, a reference circuit, a transistor, and a feedback circuit. The measurement resistor includes a first contact, a second contact, a third contact, and a fourth contact. The first contact and the second contact are located at a first end of the measurement resistor. The third contact and the fourth contact are located at a second end of the measurement resistor. A reference power (or a reference voltage) electrically connects to the reference circuit. The reference circuit and the first contact of the measurement resistor are electrically connected. The transistor includes a drain, a gate, and a source. The reference circuit and the gate of the transistor are electrically connected. One of the source and the drain of the transistor electrically connects to the second contact of the measurement resistor.

Abstract: A foam and a foaming composition are provided. The foam includes a composite material and a plurality of foam cells, wherein the foam cells are disposed in the composite material. The composite material includes a modified sulfur-containing polymer and a fluorine-containing polymer fiber, wherein a degree of orientation as defined by the ratio I110/I200 is from 1.0 to 1.3, wherein I110 is the X-ray diffraction peak intensity of (110) planes of the modified sulfur-containing polymer and I200 is the X-ray diffraction peak intensity of (200) planes of the modified sulfur-containing polymer.

Abstract: A display panel and a manufacturing method thereof are provided. The display panel includes a substrate, an active element, a driving circuit element, a first connection circuit, a second connection circuit and a conductive connector. The substrate has a first surface and a second surface opposite to the first surface. The active element is disposed on the first surface. The driving circuit element is disposed on the second surface and is overlapped with the active element. The first connection circuit is disposed on the first surface and is connected to the active element. The second connection circuit is disposed on the second surface and is connected to the driving circuit element. The conductive connector penetrates through the substrate and two ends of the conductive connector are electrically connected to the first connection circuit and the second connection circuit, respectively.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The conductive pillar is formed in one piece, the conductive pillar has a lower surface and a bottom protruding portion protruding from the lower surface, the bottom protruding portion passes through the insulating layer over the first conductive line, the bottom protruding portion is in direct contact with the first conductive line, and a first linewidth of a first portion of the first conductive line under the conductive pillar is less than a width of the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

Abstract: A method of fabricating a semiconductor substrate includes the following steps. A carrier substrate is provided, and a plasma treatment is performed on the surface of the carrier substrate. A polycrystalline semiconductor layer is formed on the surface of the carrier substrate. A rapid thermal treatment is then performed on the polycrystalline semiconductor layer. A buried dielectric layer is then formed on the polycrystalline semiconductor layer. Afterwards, a single crystalline semiconductor layer is formed on the buried dielectric layer.