Abstract: A method is provided for repairing Z-notch wear surfaces on low pressure gas turbine engine turbine blades. The method is directed to turbine blades made of superalloy Inconel 713. Powdered Inconel 713 is welded to the Z-notch wear surface by directing an Nd:YAG laser beam upon the material. The laser beam is focused and traverses the wear surface in a stich-like pattern. The method allows Inconel 713 turbine blades to be repaired with the same material in a manner that does not generate cracking in the matrix material.

Abstract: Novel Mucroslysin protein and nucleic acid molecules are disclosed. The invention provides purified Mucroslysin protein, fusion protein, antigenic peptides, and anti-Mucroslysin antibodies. The invention also provides isolated Mucroslysin nucleic acid molecule, recombinant vectors containing the Mucroslysin nucleic acid molecule, host cells containng the recombinant vector, and non-human transgenic animals in which the Mucroslysin nucleic acid molecule has been introduced.

Abstract: The present invention discloses a voltage shifter capable of interfacing between two circuitry each is operating in different voltage range. The voltage shifter comprises an input buffer for converting an external input signal switching within a high voltage range to an internal input signal switching within a low voltage range, an output driver for converting an internal output signal switching within the low voltage range to an external output signal switching within the high voltage range; and a reference voltage generator for generating a reference voltage to the input buffer and the output driver. In addition, the voltage shifter is designed such that each of the transistors within is protected against voltage breakdown so that the voltage shifter can be built by transistors using the low voltage process.

Abstract: An output buffer circuit for preconditioning an output signal at an output node so as to provide a higher speed of operation and less ground bounce noise includes an output buffer stage, a precondition feedback circuit, an output predriver, an output tristate control circuit, and an output state retention circuit. The output pre-driver with input equalization, which is also part of precondition control, combined with the output buffer stage designed with its threshold voltage matching component's input and output threshold voltage such that the output feedback, which bring the output and the input nodes of the output buffer stage together, will drive the output level to the threshold point enabled by the precondition signals before the data input signals arrive. The output buffer noise can be reduced by slowly driving output level to the output threshold point about three to four nanoseconds earlier than the data input signals arrive.

Abstract: A multiple-purpose playing set includes a basic seat supported on a rope secured to a ceiling or a frame for serving as a swing, a longitudinal plate having a central portion engageable with the basic seat for serving as a seesaw, a basin having a central portion engageably mounted on the basic seat for serving as a cradle, and at least a bar tied on the rope for serving as a high bar or as a ladder. The longitudinal plate may also be inclinedly secured on the rope having an upper end portion of the rope fixed on an upper frame or a ceiling and having a lower end portion of the rope fixed on a bottom wall or a floor for serving as a slide.

Abstract: A bipolar/CMOS ECL-to-CMOS conversion circuit for receiving ECL differential input signals and for converting the ECL input signals to CMOS complementary output signals, includes, a first output stage (20), a second output signal (22), a first base drive circuit (24), a second base drive circuit (26), a third base drive circuit (28), and a fourth base drive circuit (30). The first and second output stages are formed of bipolar transistors, and the first through fourth base drive circuits ar formed of CMOS transistors. The bipolar transistors and CMOS transistors are merged in a common semiconductor substrate in order to form the conversion circuit which has high current drive capabilities and low propagation delay regardless of variations in temperature and process corners.

Abstract: A bipolar/CMOS decoder circuit for providing a decoded output signal includes a plurality of pull-up gate circuits (14a) and a pull-down circuit (16). Each of the gate circuite (14a) is formed of a pull-up P-channel MOS transistor (P1), a pull-down N-Channel MOS transistor (N1), and a pull-up bipolar transistor (Q1). The pull-down circuit (16) is formed of a single pull-down current source, N-channel MOS transistor (N.0.). The bipolar transistors and CMOS transistors are merged in a common semiconductor substrate in order to form the decoder circuit which has a high noise margin and low pattern sensitivity even with a large number of inputs.

Abstract: A bipolar/CMOS regulator circuit for generating a CMOS gate-controlling voltage, which varies favorably with temperature, power supply voltage and process corner so as to yield a well-controlled CMOS current includes a bipolar bandgap regulator circuit portion (12) and a conversion circuit portion (14). The conversion circuit portion (14) is formed of a current mirror section (18), a current source section (20) and an output section (22).

Abstract: A bipolar/CMOS read/write control and sensing circuit is provided for use with MOS memory cells in which data can be written into and sensed in the memory cells at high speeds. The MOS memory cell is coupled with a word line and between first and second bit lines at corresponding first and second sense nodes. The control and sensing circuit includes a bit-line clamping network which is responsive to an output control signal for clamping the first and second bit lines during a read operation so as to present a low impedance thereby decreasing the read time and for unclamping of the first and second bit lines during a write operation so as to present a high impedance which reduces the write time.

Abstract: Load resistors are connected in series between the PNP portions of the SCRs and the upper word-line. The load presented to the NPN portions of the SCRs is thus a composite formed of a PNP transistor in series with a resistor. The resistor causes a downward shift of voltage due to IR drop on the ON side of the cell and provides a dramatic improvement in writing speed. During a write operation, the IR drop across the resistor on the ON side of the cell collapses as current declines, and the consequent rise in voltage is coupled to the low base line, significantly shortening the time required to raise its voltage sufficiently to securely write the cell.