Patents by Inventor Wen-Han Hung

Wen-Han Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080020523
    Abstract: A method of fabricating a metal-oxide-semiconductor transistor is provided. A first gate structure and a second gate structure are formed on a substrate. The first gate structure has a dimension greater than the second gate structure. Then, first lightly doped drain regions are formed in the substrate on two sides of the first gate structure. A lightly doped drain annealing process is performed. Next, second lightly doped drain regions are formed in the substrate on two sides of the second gate structure. First spacers are formed on the sidewalls of the first gate structure and second spacers are formed on the sidewalls of the second gate structure at the same time. Afterwards, first source/drain regions are formed in the substrate on two sides of the first spacers and second source/drain regions are formed in the substrate on two sides of the second spacers. A source/drain annealing process is performed.
    Type: Application
    Filed: July 19, 2006
    Publication date: January 24, 2008
    Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Li-Shian Jeng, Wen-Han Hung, Shyh-Fann Ting, Jing-Yi Huang, Tzyy-Ming Cheng, Chia-Wen Liang
  • Publication number: 20080020588
    Abstract: A method of forming a semiconductor device. The method comprises steps of providing a substrate having a first transistor, a second transistor and non-salicide device formed thereon and the conductive type of the first transistor is different from that of the second transistor. A buffer layer is formed over the substrate and a tensile material layer is formed over the buffer layer. A portion of the tensile material layer over the second transistor is thinned and a spike annealing process is performed. The tensile material layer is removed to expose the buffer layer over the substrate and a patterned salicide blocking layer is formed over the non-salicide device. A salicide process is performed for forming a salicide layer on a portion of the first transistor and the second transistor.
    Type: Application
    Filed: July 20, 2006
    Publication date: January 24, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Han Hung, Cheng-Tung Huang, Kun-Hsien Lee, Shyh-Fann Ting, Li-Shian Jeng, Tzyy-Ming Cheng, Chia-Wen Liang, Neng-Kuo Chen
  • Patent number: 7303962
    Abstract: A complementary metal-oxide-semiconductor (CMOS) device comprising a substrate, a first type of metal-oxide-semiconductor (MOS) transistor, a second type of MOS transistor, an etching stop layer, a first stress layer and a second stress layer is provided. The substrate has a first and a second active region. The first active region is isolated from the second active region through an isolation structure. The first type of MOS transistor is disposed in the first active region of the substrate and the second type of MOS transistor is disposed in the second active region of the substrate. The etching stop layer covers conformably the first type of MOS transistor, the second type of MOS transistor and the isolation structure. The first stress layer is disposed on the etching stop layer in the first active region and the second stress layer is disposed on the etching stop layer in the second active region.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: December 4, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Pei-Tu Chou, Min-Chieh Yang, Wen-Han Hung
  • Publication number: 20070275530
    Abstract: A semiconductor structure and a method of fabricating the same are provided. A substrate having a metal-oxide-semiconductor transistor is provided. The metal-oxide-semiconductor transistor includes a gate, a source/drain extended region, a first spacer, a liner, a source/drain and a metal silicide layer. A portion of the first spacer is removed to form a second spacer by performing an etching process. A contact etching stop layer is formed over the substrate.
    Type: Application
    Filed: May 24, 2006
    Publication date: November 29, 2007
    Inventors: Wen-Han Hung, Cheng-Tung Huang, Da-Ching Chiou, Shyh-Fann Ting, Li-Shian Jeng, Kun-Hsien Lee, Tzermin Shen, Tzyy-Ming Cheng
  • Publication number: 20070257321
    Abstract: A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an S/D extension region beside the gate structure. An opening is formed in the substrate beside the spacer, and then an S/D region is formed in or on the substrate at the bottom of the opening. A metal silicide layer is formed on the S/D region and the gate structure, and then a stress layer is formed over the substrate.
    Type: Application
    Filed: July 13, 2007
    Publication date: November 8, 2007
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Wen-Han Hung, Li-Shian Jeng, Tzyy-Ming Cheng
  • Publication number: 20070252218
    Abstract: A semiconductor device is provided herein, which includes a substrate having a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The semiconductor device further includes a first stress layer and a second stress layer. The first stress layer is disposed on the first-type MOS transistor, or on the first-type MOS transistor and the I/O second-type MOS transistor. The second stress layer is disposed on the core second-type MOS transistor.
    Type: Application
    Filed: July 12, 2007
    Publication date: November 1, 2007
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Tzyy-Ming Cheng, Chia-Wen Lang
  • Patent number: 7288822
    Abstract: A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor is disposed on the second well, including a gate structure on the second well and a strained layer of the first conductivity type in an opening in the second well beside the gate structure. The difference between the lattice parameter of a portion of the strained layer near the bottom of the opening and that of the substrate is less than the difference between the lattice parameter of a portion of the strained layer apart from the bottom of the opening and that of the substrate. The second MOS transistor is disposed on the first well.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: October 30, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Wen-Han Hung, Li-Shian Jeng, Kun-Hsien Lee, Tzyy-Ming Cheng, Jing-Chang Wu, Tzermin Shen
  • Publication number: 20070238235
    Abstract: A method for fabricating a semiconductor device is provided. First, a substrate is provided, and a first-type MOS (metallic oxide semiconductor) transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor are formed on the substrate. Then, a first stress layer is formed to overlay the substrate, the first-type MOS transistor, the I/O second-type MOS transistor, and the core second-type MOS transistor. Then, at least the first stress layer on the core second-type MOS transistor is removed to reserve at least the first stress layer on the first-type MOS transistor. Finally, a second stress layer is formed on the core second-type MOS transistor.
    Type: Application
    Filed: April 7, 2006
    Publication date: October 11, 2007
    Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Tzyy-Ming Cheng, Chia-Wen Liang
  • Publication number: 20070235770
    Abstract: A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor is disposed on the second well, including a gate structure on the second well and a strained layer of the first conductivity type in an opening in the second well beside the gate structure. The difference between the cell parameter of a portion of the strained layer near the bottom of the opening and that of the substrate is less than the difference between the cell parameter of a portion of the strained layer apart from the bottom of the opening and that of the substrate. The second MOS transistor is disposed on the first well.
    Type: Application
    Filed: April 7, 2006
    Publication date: October 11, 2007
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Wen-Han Hung, Li-Shian Jeng, Kun-Hsien Lee, Tzyy-Ming Cheng, Jing-Chang Wu, Tzermin Shen
  • Publication number: 20070238241
    Abstract: A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor is disposed on the second well, including a gate structure on the second well and a strained layer of the first conductivity type in an opening in the second well beside the gate structure. The difference between the cell parameter of a portion of the strained layer near the bottom of the opening and that of the substrate is less than the difference between the cell parameter of a portion of the strained layer apart from the bottom of the opening and that of the substrate. The second MOS transistor is disposed on the first well.
    Type: Application
    Filed: May 30, 2007
    Publication date: October 11, 2007
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Wen-Han Hung, Li-Shian Jeng, Kun-Hsien Lee, Tzyy-Ming Cheng, Jing-Chang Wu, Tzermin Shen
  • Publication number: 20070238242
    Abstract: A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an S/D extension region beside the gate structure. An opening is formed in the substrate beside the spacer, and then an S/D region is formed in or on the substrate at the bottom of the opening. A metal silicide layer is formed on the S/D region and the gate structure, and then a stress layer is formed over the substrate.
    Type: Application
    Filed: April 6, 2006
    Publication date: October 11, 2007
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Wen-Han Hung, Li-Shian Jeng, Tzyy-Ming Cheng
  • Publication number: 20070187727
    Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.
    Type: Application
    Filed: February 16, 2006
    Publication date: August 16, 2007
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Wen-Han Hung, Tzyy-Ming Cheng, Tzer-Min Shen, Yi-Chung Sheng
  • Publication number: 20070128783
    Abstract: A semiconductor substrate having a first active region and a second active region for fabricating a first transistor and a second transistor is provided. A first gate structure and a second gate structure are formed on the first active region and the second active region and a first spacer is formed surrounding the first gate structure and the second gate structure. A source/drain region for the first transistor and the second transistor is formed. The first spacer is removed from the first gate structure and the second gate structure and a cap layer is disposed on the first transistor and the second transistor and the cap layer covering the second transistor is removed thereafter. An etching process is performed to form a recess in the substrate surrounding the second gate structure. An epitaxial layer is formed in the recess and the cap layer is removed from the first transistor.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 7, 2007
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Jing-Chang Wu, Kun-Hsien Lee, Wen-Han Hung, Li-Shian Jeng, Tzer-Min Shen, Tzyy-Ming Cheng, Nien-Chung Li
  • Publication number: 20070111452
    Abstract: A complementary metal-oxide-semiconductor (CMOS) device comprising a substrate, a first type of metal-oxide-semiconductor (MOS) transistor, a second type of MOS transistor, an etching stop layer, a first stress layer and a second stress layer is provided. The substrate has a first and a second active region. The first active region is isolated from the second active region through an isolation structure. The first type of MOS transistor is disposed in the first active region of the substrate and the second type of MOS transistor is disposed in the second active region of the substrate. The etching stop layer covers conformably the first type of MOS transistor, the second type of MOS transistor and the isolation structure. The first stress layer is disposed on the etching stop layer in the first active region and the second stress layer is disposed on the etching stop layer in the second active region.
    Type: Application
    Filed: November 16, 2005
    Publication date: May 17, 2007
    Inventors: Pei-Yu Chou, Min-Chieh Yang, Wen-Han Hung
  • Publication number: 20070111420
    Abstract: A complementary metal-oxide-semiconductor (CMOS) device comprising a substrate, a first type of metal-oxide-semiconductor (MOS) transistor, a second type of MOS transistor, an etching stop layer, a first stress layer and a second stress layer is provided. The substrate has a first active region and a second active region. The first active region is isolated from the second active region through an isolation structure. The first type of MOS transistor is disposed in the first active region of the substrate; the second type of MOS transistor is disposed in the second active region of the substrate. The etching stop layer covers conformably the first type of MOS transistor, the second type of MOS transistor and the isolation structure. The first stress layer is disposed on the etching stop layer in the first active region and the second stress layer is disposed on the etching stop layer in the second active region.
    Type: Application
    Filed: July 13, 2006
    Publication date: May 17, 2007
    Inventors: Pei-Yu Chou, Min-Chieh Yang, Wen-Han Hung
  • Publication number: 20060199305
    Abstract: A method for fabricating an ultra-high tensile-stressed nitride film is disclosed. A PECVD process is first performed to deposit a transitional silicon nitride film over a substrate. The transitional silicon nitride film has a first concentration of hydrogen atoms. The transitional silicon nitride film is subjected to UV curing process for reducing the first concentration of hydrogen atoms to a second concentration of hydrogen atoms.
    Type: Application
    Filed: November 24, 2005
    Publication date: September 7, 2006
    Inventors: Neng-Kuo Chen, Teng-Chun Tsai, Chien-Chung Huang, Tsai-Fu Chen, Wen-Han Hung
  • Patent number: 6740471
    Abstract: A method of improving photoresist adhesion in a reworked device, including the following steps. A semiconductor structure having an upper exposed metal layer is provided. An ARC layer is formed over the upper exposed metal layer. The ARC layer having an upper surface. A first photoresist layer is formed upon the ARC layer. The first photoresist layer is removed by a rework process. The ARC layer upper surface is roughened to form a roughened ARC layer upper surface. A second photoresist layer is formed upon the roughened ARC layer upper surface whereby adhesion of the second photoresist layer to the ARC layer is improved.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: May 25, 2004
    Inventors: Gau-Ming Lu, Dowson Jang, Wen-Han Hung, Yeong-Rong Chang
  • Patent number: 6238965
    Abstract: A method for forming a titanium dioxide layer is disclosed. The method includes the steps of providing a titanium-containing material, adding an acid substance to the titanium-containing material to form a mixture, and exposing the device to the mixture to form the titanium dioxide layer thereon. Such a method can be applied for forming a titanium dioxide layer on a semiconductor device, a silicon substrate, an integrated circuit, a photoelectric device, etc.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: May 29, 2001
    Assignee: Winbond Electronics Corp.
    Inventors: Ming-Kwei Lee, Wen-Han Hung
  • Patent number: 6153539
    Abstract: A liquid phase deposition method for growing a titanium dioxide on the gallium arsenide substrate is disclosed. Wherein the solution of hexafluorotitanic acid (H.sub.2 TiF.sub.6) is added with nitric acid (HNO.sub.3) and boric acid (H.sub.3 BO.sub.3) or only added with a nitric acid. Thus a titanium dioxide film is grown on the gallium arsenide substrate which is the most important material of semiconductor. The refractive index will achieve to a value of 2.5. The growth rate can be exactly controlled by the concentration of the nitric acid. The present invention has the advantages of lower cost and low growing temperature. Not only the industrial necessity is satisfied, but also the disadvantages from other growing process having a high cost and expensive equipment is avoided. Thus, the present invention is potentially used in the process of integrated circuits, such as being used in the memory structure with a higher dielectric constant.
    Type: Grant
    Filed: March 11, 1999
    Date of Patent: November 28, 2000
    Assignee: National Science Council of Republic of China
    Inventors: Ming-Kwei Lee, Wen-Han Hung