Patents by Inventor Wen-Hann Wang
Wen-Hann Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8745306Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: GrantFiled: August 21, 2012Date of Patent: June 3, 2014Assignee: Intel CorporationInventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
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Publication number: 20120317328Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: ApplicationFiled: August 21, 2012Publication date: December 13, 2012Inventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
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Patent number: 8255605Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BICS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: GrantFiled: March 30, 2011Date of Patent: August 28, 2012Assignee: Intel CorporationInventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H Hofsheier, Nitin Y. Borkar
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Publication number: 20110185101Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: ApplicationFiled: March 30, 2011Publication date: July 28, 2011Inventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
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Patent number: 7930464Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: GrantFiled: August 28, 2009Date of Patent: April 19, 2011Assignee: Intel CorporationInventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
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Publication number: 20090319717Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: ApplicationFiled: August 28, 2009Publication date: December 24, 2009Inventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
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Patent number: 7603508Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: GrantFiled: January 14, 2008Date of Patent: October 13, 2009Assignee: Intel CorporationInventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
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Publication number: 20080114919Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: ApplicationFiled: January 14, 2008Publication date: May 15, 2008Inventors: Linda Rankin, Paul Pierce, Gregory Dermer, Wen-Hann Wang, Kai Cheng, Richard Hofsheier, Nitin Borkar
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Patent number: 7343442Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: GrantFiled: June 6, 2006Date of Patent: March 11, 2008Assignee: Intel CorporationInventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
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Publication number: 20070106833Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: ApplicationFiled: June 6, 2006Publication date: May 10, 2007Inventors: Linda Rankin, Paul Pierce, Gregory Dermer, Wen-Hann Wang, Kai Cheng, Richard Hofsheier, Nitin Borkar
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Patent number: 7076613Abstract: The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor computer systems. Some embodiments of the invention comprise an invalidation history table to record the line addresses of cache lines invalidated through dirty or clean invalidation, and which is used such that invalidated cache lines recorded in an invalidation history table are reloaded into cache by monitoring the bus for cache line addresses of cache lines recorded in the invalidation history table. In some further embodiments, a write-back bit associated with each L2 cache entry records when either a hit to the same line in another processor is detected or when the same line is invalidated in another processor's cache, and the system broadcasts write-backs from the selected local cache only when the line being written back has a write-back bit that has been set.Type: GrantFiled: January 21, 2004Date of Patent: July 11, 2006Assignee: Intel CorporationInventors: Jih-Kwon Peir, Steve Y. Zhang, Scott H. Robinson, Konrad Lai, Wen-Hann Wang
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Patent number: 7058750Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: GrantFiled: May 10, 2000Date of Patent: June 6, 2006Assignee: Intel CorporationInventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
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Publication number: 20040268054Abstract: The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor computer systems. Some embodiments of the invention comprise an invalidation history table to record the line addresses of cache lines invalidated through dirty or clean invalidation, and which is used such that invalidated cache lines recorded in an invalidation history table are reloaded into cache by monitoring the bus for cache line addresses of cache lines recorded in the invalidation history table. In some further embodiments, a write-back bit associated with each L2 cache entry records when either a hit to the same line in another processor is detected or when the same line is invalidated in another processor's cache, and the system broadcasts write-backs from the selected local cache only when the line being written back has a write-back bit that has been set.Type: ApplicationFiled: January 21, 2004Publication date: December 30, 2004Applicant: Intel CorporationInventors: Jih-Kwon Peir, Steve Y. Zhang, Scott H. Robinson, Konrad Lai, Wen-Hann Wang
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Patent number: 6725341Abstract: The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor computer systems. Some embodiments of the invention comprise an invalidation history table to record the line addresses of cache lines invalidated through dirty or clean invalidation, and which is used such that invalidated cache lines recorded in an invalidation history table are reloaded into cache by monitoring the bus for cache line addresses of cache lines recorded in the invalidation history table. In some further embodiments, a write-back bit associated with each L2 cache entry records when either a hit to the same line in another processor is detected or when the same line is invalidated in another processor's cache, and the system broadcasts write-backs from the selected local cache only when the line being written back has a write-back bit that has been set.Type: GrantFiled: June 28, 2000Date of Patent: April 20, 2004Assignee: Intel CorporationInventors: Jih-Kwon Peir, Steve Y. Zhang, Scott H. Robinson, Konrad Lai, Wen-Hann Wang
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Publication number: 20030004974Abstract: According to the invention, an apparatus and method are disclosed for configurable system monitoring for dynamic optimization of program execution. According to one embodiment, an event monitoring apparatus for dynamic optimization comprises an event monitor to capture profiles of events that occur in the processing of an application by a microprocessor; an interface to a software component; monitor control vectors to direct the operation of the event monitor; and a profile buffer. According to the embodiment, the events to be monitored are selected by the software component. Profiles of the selected events are captured and stored in the profile buffer. The profiles are made available to a handler routine selected by the software component, which processes the profiles to identify regions of the application for optimization and invokes optimizers to optimize the identified regions.Type: ApplicationFiled: September 28, 2001Publication date: January 2, 2003Inventors: Hong Wang, Dong-Yuan Chen, John Shen, Wen-Hann Wang, Oren Gershon, Gadi Reuven Ziv
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Publication number: 20030005423Abstract: According to the invention, hardware assisted dynamic optimization of program execution is disclosed. According to one embodiment, an application process executed by a microprocessor is optimized by selecting one or more microarchitecture events relating to the execution of the application process to be monitored by one or more hardware monitors; establishing parameters regarding the monitoring of the microarchitecture events by setting one or more monitor control vectors; processing profile data captured by the hardware monitors regarding the occurrence of the microarchitecture events; identifying a region of interest in the application process for optimization based at least in part on the captured profile data; and optimizing the region of interest in the application process.Type: ApplicationFiled: September 28, 2001Publication date: January 2, 2003Inventors: Dong-Yuan Chen, Hong Wang, Jesse Fang, John Shen, Wen-Hann Wang, Bernard Lint
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Patent number: 6006299Abstract: In a computer system, an apparatus for handling lock conditions wherein a first instruction executed by a first processor processes data that is common to a second processor while the second processor is locked from simultaneously executing a second instruction that also processes this same data. A lock bit is set when the first processor begins execution of the first instruction. Thereupon, the second processor is prevented from executing its instruction until the first processor has completed its processing of the shared data. Hence, the second processor queues its request in a buffer. The lock bit is cleared after the first processor has completed execution of its instruction. The first processor then checks the buffer for any outstanding requests. In response to the second processor's queued request, the first processor transmits a signal to the second processor indicating that the data is now not locked.Type: GrantFiled: March 1, 1994Date of Patent: December 21, 1999Assignee: Intel CorporationInventors: Wen-Hann Wang, Konrad K. Lai, Gurbir Singh, Mandar S. Joshi, Nitin V. Sarangdhar, Matthew A. Fisch
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Patent number: 5956746Abstract: The present invention includes a computer system having an on-processor predictor tag array, an off-processor cache memory, and comparison circuitry. The on-processor predictor tag array contains first portions of tag information for multiple ways and multiple sets. The off-processor cache memory includes memory locations to store data and second portions of tag information. The comparison circuitry makes a first comparison of a first portion of an address with the first portions of tag information for the ways of one of the sets and uses results of the first comparison in predicting which of the ways, if any, correspond to the address. The comparison circuitry also makes a second comparison of the second portion of the address with sections of the second portions of tag information identified by the predicted way and the address.Type: GrantFiled: August 13, 1997Date of Patent: September 21, 1999Assignee: Intel CorporationInventor: Wen-Hann Wang
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Patent number: 5829038Abstract: A system and method for reducing the number of writeback operations performed by level two (L2) or higher level cache memories in a microprocessor system having an integrated hierarchical cache structure. Writeback operations of modified victim lines in L2 or higher level caches are cancelled if an associated cache line, having a "modified" status, is located in a lower level cache. In one embodiment of the present invention, writeback operations of modified victim lines in L2 or higher level caches are also cancelled if an associated cache line, having a "clean" status, is located in a lower level cache.Type: GrantFiled: June 20, 1996Date of Patent: October 27, 1998Assignee: Intel CorporationInventors: Quinn Merrell, Wen-Hann Wang
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Patent number: 5809524Abstract: A method and apparatus for cache memory replacement line identification have a cache interface which provides a communication interface between a cache memory and a controller for the cache memory. The interface includes an address bus, a data bus, and a status bus. The address bus transfers requested addresses from the controller to the cache memory. The data bus transfers data associated with requested addresses from the controller to the cache memory, and also transfers replacement line addresses from the cache memory to the controller. The status bus transfers status information associated with the requested addresses from the cache memory to the controller which indicate whether the requested addresses are contained in the cache memory. In one embodiment, the data bus also transfers cache line data associated with a requested address from the cache memory to the controller when the requested address hits the cache memory.Type: GrantFiled: March 24, 1997Date of Patent: September 15, 1998Assignee: Intel CorporationInventors: Gurbir Singh, Wen-Hann Wang, Michael W. Rhodehamel, John M. Bauer, Nitin V. Sarangdhar