Abstract: A computer system comprising a plurality of caching agents with a cache hierarchy, the caching agents sharing memory across a system bus and issuing memory access requests in accordance with a protocol wherein a line of a cache has a present state comprising one of a plurality of line states. The plurality of line states includes a modified (M) state, wherein a line of a first caching agent in M state has data which is more recent than any other copy in the system; an exclusive (E) state, wherein a line in E state in a first caching agent is the only one of the agents in the system which has a copy of the data in a line of the cache, the first caching agent modifying the data in the cache line independent of other said agents coupled to the system bus; a shared (S) state, wherein a line in S state indicates that more than one of the agents has a copy of the data in the line; and an invalid (I) state indicating that the line does not exist in the cache.

Abstract: A method and apparatus for transferring information between a processor and a memory system utilizing a chunk write buffer, where read and write requests to the L2 cache memory are controlled by the processor. The cache line associated with each such request is larger than the interface coupling the L2 cache memory and the processor. Read requests are returned from the L2 cache memory to the processor in burst fashion. Write requests are transferred from the processor to the L2 cache memory during clock cycles in which the processor does not require the interface for a read request. Write requests need not be transferred in burst fashion; rather, a portion of the write request corresponding to the size of the interface, referred to as a chunk, is transferred from the processor to the L2 cache memory and stored temporarily in the chunk write buffer.

Abstract: A cache memory with reduced request-blocking blocks requests from being accepted by the cache memory based on the types of requests the cache is already servicing. A request which hits the cache memory or a request which misses the cache memory but does not conflict with any requests already being serviced is not blocked. A request which misses the cache memory and also conflicts with a request(s) already being serviced causes the request to be blocked. In one embodiment, conflicts for write requests are determined by checking whether the cache is already retrieving a cache line from system memory for a request which maps into the same cache set as the write request. If such a request exists, then a conflict occurs. In this embodiment, conflicts for read requests are determined by checking whether the cache is already servicing an outstanding request to memory for the same address. If so, then a conflict occurs.

Abstract: A protection update buffer in conjunction with a cache memory that stores data, protection information and data line tags. The protection update buffer also stores cache address tags. By storing cache tags in the protection update buffer, the protection update buffer may alert the cache memory of lines that have had protection bits change. Also, by further storing data protection information in the protection update buffer, it is possible for the protection update buffer to provide correct protection information for cached data. If writing a tag and/or data protection information to the protection update buffer causes an overflow of the protection update buffer, then the associated cache is flushed and the entries of the protection update buffer are cleared.

Abstract: In a computer system having a plurality of processors with internal caches, a method for handling race conditions arising when multiple processors simultaneously write to a particular cache line. Initially, a determination is made as to whether the cache line is in an exclusive, modified, invalid, or shared state. If the cache line is in either the exclusive or modified state, the cache line is written to and then set to the modified state. If the cache line is in the invalid state, a Bus-Read-Invalidate operation is performed. However, if the cache line is in the shared state and multiple processors initiate Bus-Write-Invalidate operations, the invalidation request belonging to the first processor is allowed to complete. Thereupon, the cache line is sent to the exclusive state, data is updated, and the cache line is set to the modified state. The second processor receives a second cache line, updates this second cache line, and sets the second cache line to the modified state.

Abstract: A two-way set-associative cache memory includes both a set array and a data array in one embodiment. The data array comprises multiple elements, each of which can contain a cache line. The set array comprises multiple sets, with each set in the set array corresponding to an element in the data array. Each set in the set array contains information which indicates whether an address received by the cache memory matches the cache line contained in its corresponding element of the data array. The information stored in each set includes a tag and a state. The tag contains a reference to one of the cache lines in the data array. If the tag of a particular set matches the address received by the cache memory, then the cache line associated with that particular set is the requested cache line. The state of a particular set indicates the number of cache lines mapped into that particular set.

Abstract: A system and method for managing caches in a multiprocessor having multiple levels of caches. An inclusion architecture and procedure are defined through which the L2 caches shield the L1 caches from extraneous communication at the L2, such as main memory and I/O read/write operations. Essential inclusion eliminates special communication from the L1 cache to the L2, yet maintains adequate knowledge at the L2, regarding the contents of the L1, to minimize L1 invalidations. Processor performance is improved by the reduced communication and the decreased number of invalidations. The processors and L1 caches practice a store-in policy. The L2 cache uses inclusion bits to designate by cache line a relationship between the line of data in the L2 cache and the corresponding lines as they exist in the associated L1 caches. Communication and invalidations are reduced through a selective setting/resetting of the inclusion bits and related L2 interrogation practice.