Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.

Abstract: A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.

Abstract: A supported metallocene catalyst includes a carrier and a metallocene component. The carrier includes an inorganic oxide particle and an alkyl aluminoxane material. The inorganic oxide particle includes at least one inorganic oxide compound selected from the group consisting of an oxide of Group 3A and an oxide of Group 4A. The alkyl aluminoxane material includes an alkyl aluminoxane compound and an alkyl aluminum compound that is present in amount ranging from greater than 0.01 wt % to less than 14 wt % base on 100 wt % of the alkyl aluminoxane material. The metallocene component is supported on the carrier, and includes one of a metallocene compound containing a metal from Group 3B, a metallocene compound containing a metal from Group 4B, and a combination thereof. A method for preparing the supported metallocene catalyst and a method for preparing polyolefin using the supported metallocene catalyst are also disclosed.

Abstract: An adaptor includes non-volatile memory that stores a scan engine. A removable storage device is connected to the adaptor, which in turn is connected to a host computer. Files being copied between the removable storage device and the host computer through the adaptor are scanned for malware using the scan engine.

Abstract: A NVM cell structure includes a semiconductor substrate having a first conductivity type, a first well region having a second conductivity type, a floating gate transistor and an erase gate region. The first well region is disposed on a first OD region of the semiconductor substrate. The erase gate region disposed on a second OD region of the semiconductor substrate includes a first doped region and at least one second doped region having the second conductivity type. The first doped region is disposed in semiconductor substrate and covers the second OD region, and the second doped region is disposed in the first doped region. The first doped region encompasses the second doped region, and a doping concentration of the second doped region is larger than a doping concentration of the first doped region.

Abstract: A NVM cell structure includes a semiconductor substrate having a first conductivity type, a first well region having a second conductivity type, a floating gate transistor and an erase gate region. The first well region is disposed on a first OD region of the semiconductor substrate. The erase gate region disposed on a second OD region of the semiconductor substrate includes a first doped region and at least one second doped region having the second conductivity type. The first doped region is disposed in semiconductor substrate and covers the second OD region, and the second doped region is disposed in the first doped region. The first doped region encompasses the second doped region, and a doping concentration of the second doped region is larger than a doping concentration of the first doped region.

Abstract: A NVM cell structure includes a semiconductor substrate having a first conductivity type, a first well region having a second conductivity type, a floating gate transistor and an erase gate region. The first well region is disposed on a first OD region of the semiconductor substrate. The erase gate region disposed on a second OD region of the semiconductor substrate includes a first doped region and at least one second doped region having the second conductivity type. The first doped region is disposed in semiconductor substrate and covers the second OD region, and the second doped region is disposed in the first doped region. The first doped region encompasses the second doped region, and a doping concentration of the second doped region is larger than a doping concentration of the first doped region.

Abstract: An integrated capacitance sensing module includes a silicon substrate, a first and a second and a third interlayer dielectric layers, plural conducting layers, a shielding layer, a lower and a upper sensing electrode layers, a protective coating layer. An embedded memory and a sensing circuit are constructed in the silicon substrate. The first interlayer dielectric layer covers the silicon substrate. The plural conducting layers are formed over the first interlayer dielectric layer. The shielding layer is formed over the plural conducting layers. The second interlayer dielectric layer covers the shielding layer. The lower sensing electrode layer is formed over the second interlayer dielectric layer. The third interlayer dielectric layer is formed over the lower sensing electrode layer. The upper sensing electrode layer is formed over the third interlayer dielectric layer. The protective coating layer covers the upper sensing electrode layer.

Abstract: An array structure of a single-poly nonvolatile memory includes a first MTP section, a first OTP section and a ROM section. The first MTP section includes a plurality of MTP cells, the first OTP section includes a plurality of OTP cells and the first ROM section includes a plurality of ROM cells. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The first OTP section is connected to a second word line, a second source line and the plurality of bit lines shared with the first MTP section. The first ROM section is connected to a third word line, a third source line and the plurality of bit lines shared with the first MTP section.

Abstract: An array structure of a single-poly nonvolatile memory includes a first MTP section and a first OTP section. The first MTP section includes a plurality of MTP cells and the first OTP section includes a plurality of OTP cells. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The first OTP section is connected to a second word line, a second source line and the plurality of bit lines shared with the first MTP section.

Abstract: An array structure of a single-poly nonvolatile memory includes a first MTP section and a first OTP section. The first MTP section includes a plurality of MTP cells and the first OTP section includes a plurality of OTP cells. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The first OTP section is connected to a second word line, a second source line and the plurality of bit lines shared with the first MTP section.

Abstract: An array structure of a single-poly nonvolatile memory includes a first MTP section, a first OTP section and a ROM section. The first MTP section includes a plurality of MTP cells, the first OTP section includes a plurality of OTP cells and the first ROM section includes a plurality of ROM cells. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The first OTP section is connected to a second word line, a second source line and the plurality of bit lines shared with the first MTP section. The first ROM section is connected to a third word line, a third source line and the plurality of bit lines shared with the first MTP section.

Abstract: An array structure of a single-poly nonvolatile memory includes a first and a second MTP sections, a first and a second OTP sections. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The second MTP section is connected to a second word line, a second source line and shares the first erase line and the plurality of bit lines with the first MTP section. The first OTP section is connected to a third word line and shares the first source line and the plurality of bit lines with the first MTP section. The second OTP section is connected to a fourth word line, a third source line, and shares the plurality of bit lines with the first MTP section, the second MTP section and the third OTP section.

Abstract: An array structure of a single-poly nonvolatile memory includes a first and a second MTP sections, a first and a second OTP sections. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The second MTP section is connected to a second word line, a second source line and shares the first erase line and the plurality of bit lines with the first MTP section. The first OTP section is connected to a third word line and shares the first source line and the plurality of bit lines with the first MTP section. The second OTP section is connected to a fourth word line, a third source line, and shares the plurality of bit lines with the first MTP section, the second MTP section and the third OTP section.

Abstract: An array structure of a single-poly nonvolatile memory includes a first and a second MTP sections, a first and a second OTP sections. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The second MTP section is connected to a second word line, a second source line and shares the first erase line and the plurality of bit lines with the first MTP section. The first OTP section is connected to a third word line and shares the first source line and the plurality of bit lines with the first MTP section. The second OTP section is connected to a fourth word line, a third source line, and shares the plurality of bit lines with the first MTP section, the second MTP section and the third OTP section.

Abstract: A NVM cell structure includes a semiconductor substrate having a first conductivity type, a first well region having a second conductivity type, a floating gate transistor and an erase gate region. The first well region is disposed on a first OD region of the semiconductor substrate. The erase gate region disposed on a second OD region of the semiconductor substrate includes a first doped region and at least one second doped region having the second conductivity type. The first doped region is disposed in semiconductor substrate and covers the second OD region, and the second doped region is disposed in the first doped region. The first doped region encompasses the second doped region, and a doping concentration of the second doped region is larger than a doping concentration of the first doped region.

Abstract: An integrated capacitance sensing module includes a silicon substrate, a first and a second and a third interlayer dielectric layers, plural conducting layers, a shielding layer, a lower and a upper sensing electrode layers, a protective coating layer. An embedded memory and a sensing circuit are constructed in the silicon substrate. The first interlayer dielectric layer covers the silicon substrate. The plural conducting layers are formed over the first interlayer dielectric layer. The shielding layer is formed over the plural conducting layers. The second interlayer dielectric layer covers the shielding layer. The lower sensing electrode layer is formed over the second interlayer dielectric layer. The third interlayer dielectric layer is formed over the lower sensing electrode layer. The upper sensing electrode layer is formed over the third interlayer dielectric layer. The protective coating layer covers the upper sensing electrode layer.

Abstract: An array structure of a single-poly nonvolatile memory includes a first and a second MTP sections, a first and a second OTP sections. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The second MTP section is connected to a second word line, a second source line and shares the first erase line and the plurality of bit lines with the first MTP section. The first OTP section is connected to a third word line and shares the first source line and the plurality of bit lines with the first MTP section. The second OTP section is connected to a fourth word line, a third source line, and shares the plurality of bit lines with the first MTP section, the second MTP section and the third OTP section.

Abstract: An erasable programmable single-poly nonvolatile memory includes a substrate structure; a first PMOS transistor comprising a select gate, a first source/drain region, and a second source/drain region, wherein the select gate is connected to a select gate voltage, and the first source/drain region is connected to a source line voltage; a second PMOS transistor comprising the second source/drain region, a third source/drain region, and a floating gate, wherein the third source/drain region is connected to a bit line voltage and the first, second and third source/drain regions are constructed in a N-well region; and an erase gate region adjacent to the floating gate, wherein the erase gate region comprises a n-type source/drain region connected to an erase line voltage and a P-well region; wherein the N-well region and the P-well region are formed in the substrate structure.

Abstract: An erasable programmable single-poly nonvolatile memory includes a substrate structure; a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region, wherein the channel region is formed in a N-well region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region and the erase gate region comprises a n-type source/drain region connected to an erase line voltage and a P-well region. The N-well and P-well region are formed in the substrate structure. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.