Abstract: An erasable programmable single-poly nonvolatile memory includes a substrate structure; a first PMOS transistor comprising a select gate, a first source/drain region, and a second source/drain region, wherein the select gate is connected to a select gate voltage, and the first source/drain region is connected to a source line voltage; a second PMOS transistor comprising the second source/drain region, a third source/drain region, and a floating gate, wherein the third source/drain region is connected to a bit line voltage and the first, second and third source/drain regions are constructed in a N-well region; and an erase gate region adjacent to the floating gate, wherein the erase gate region comprises a n-type source/drain region connected to an erase line voltage and a P-well region; wherein the N-well region and the P-well region are formed in the substrate structure.

Abstract: An erasable programmable single-poly nonvolatile memory includes a substrate structure; a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region, wherein the channel region is formed in a N-well region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region and the erase gate region comprises a n-type source/drain region connected to an erase line voltage and a P-well region. The N-well and P-well region are formed in the substrate structure. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.

Abstract: An erasable programmable single-poly nonvolatile memory includes a substrate structure; a first PMOS transistor comprising a select gate, a first source/drain region, and a second source/drain region, wherein the select gate is connected to a select gate voltage, and the first source/drain region is connected to a source line voltage; a second PMOS transistor comprising the second source/drain region, a third source/drain region, and a floating gate, wherein the third source/drain region is connected to a bit line voltage and the first, second and third source/drain regions are constructed in a N-well region; and an erase gate region adjacent to the floating gate, wherein the erase gate region comprises a n-type source/drain region connected to an erase line voltage and a P-well region; wherein the N-well region and the P-well region are formed in the substrate structure.

Abstract: An erasable programmable single-poly nonvolatile memory includes a substrate structure; a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region, wherein the channel region is formed in a N-well region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region and the erase gate region comprises a n-type source/drain region connected to an erase line voltage and a P-well region. The N-well and P-well region are formed in the substrate structure. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.

Abstract: A package having a light-emitting element includes a substrate having a light-emitting element disposed thereon, an insulating layer formed on the substrate and having an opening for exposing the light-emitting element, a florescent layer formed in the opening of the insulating layer for encapsulating the light-emitting element, and a transparent material formed on the florescent layer and the insulating layer. As such, a specific space can be defined by the insulating layer for exposing the light-emitting element and forming the fluorescent layer, thereby overcoming the problem of non-uniform coating of phosphor powder as encountered in prior techniques.

Abstract: A light-emitting diode (LED) package structure and a packaging method thereof are provided. The packaging method includes: forming first conductive layers on a silicon substrate, and forming a reflection cavity and electrode via holes from a top surface of the silicon substrate; forming a reflection layer on predetermined areas of a surface of the reflection cavity, and forming second conductive layers and metal layers on surfaces of the electrode via holes; and mounting a chip and forming an encapsulant, so as to fabricate the LED package structure. In the present invention, there is no need to perform at least two plating processes for connecting upper and lower conductive layers of the silicon substrate in the electrode via holes, and the problem of poor connection of the conductive layers in the electrode via holes can be avoided, thereby making the fabrication processes simplified and time-effective and also improving the overall production yield.

Abstract: A package having a light-emitting element includes a substrate having a light-emitting element disposed thereon, an insulating layer formed on the substrate and having an opening for exposing the light-emitting element, a florescent layer formed in the opening of the insulating layer for encapsulating the light-emitting element, and a transparent material formed on the florescent layer and the insulating layer. As such, a specific space can be defined by the insulating layer for exposing the light-emitting element and forming the fluorescent layer, thereby overcoming the problem of non-uniform coating of phosphor powder as encountered in prior techniques.

Abstract: A package includes at least a chip encapsulated by an encapsulant. Conductive bumps are disposed on a first surface of the chip, for a circuit board to be disposed thereon. A phosphor layer is formed on a second surface of the chip opposing the first surface. The package further comprises a light-pervious mask that covers the phosphor layer. Since the phosphor layer and the light-pervious mask are directly formed on the chip, the chip is prevented from being disposed in the groove of the substrate. As a result, the wet etching process is omitted, and the fabrication cost is reduced. A method of fabricating the package is also provided.

Abstract: A high-voltage selecting circuit generates an output voltage with no voltage drop by means of an auxiliary NMOS transistor turning on the corresponding selecting PMOS transistor of the high-voltage selecting circuit when the voltage levels of a first input voltage and a second input voltage are equal. In addition, when one of the first input voltage and the second input voltage is higher than the other one, the high-voltage selecting circuit avoids the leakage current by means of an auxiliary PMOS transistor turning off the corresponding selecting PMOS transistor of the high-voltage selecting circuit. In this way, the high-voltage selecting circuit can correctly generate the output voltage according to the first input voltage and the second input voltage, and avoid the leakage current at the same time.

Abstract: A high-voltage selecting circuit generates an output voltage with no voltage drop by means of an auxiliary NMOS transistor turning on the corresponding selecting PMOS transistor of the high-voltage selecting circuit when the voltage levels of a first input voltage and a second input voltage are equal. In addition, when one of the first input voltage and the second input voltage is higher than the other one, the high-voltage selecting circuit avoids the leakage current by means of an auxiliary PMOS transistor turning off the corresponding selecting PMOS transistor of the high-voltage selecting circuit. In this way, the high-voltage selecting circuit can correctly generate the output voltage according to the first input voltage and the second input voltage, and avoid the leakage current at the same time.

Abstract: A scleral buckling band and a method for making the same are described. The scleral buckling band is used for an ophthalmic operation, which is biocompatible and has a slender cylindrical structure formed by a decomposable and absorbable material. When being implanted into human body, the scleral buckling band is degraded and absorbed by the human body, without causing any immune response. After the patient is recovered, the scleral buckling band does not need to be taken out through another operation. Meanwhile, the decomposition rate of the scleral buckling band within the human body can be controlled through different preparation manners, so as to cater to different recovery speeds of different patients. Furthermore, the scleral buckling band contains different medicine, and after being implanted into human body and being decomposed, the scleral buckling band releases different specific medicine as time elapsed.

Abstract: A semiconductor package and a substrate structure thereof are provided. A solder mask layer applied on the substrate structure is formed with outwardly extended openings corresponding to corner portions of a chip mounting area of the substrate structure. When a flip-chip semiconductor chip is mounted on the chip mounting area and an underfilling process is performed, an underfill material can fill a gap between the flip-chip semiconductor chip and the substrate structure, and effectively fill the outwardly extended openings of the solder mask layer corresponding to the corner portions of the chip mounting area so as to provide sufficient protection for corners of the flip-chip semiconductor chip and prevent delamination at the corners of the flip-chip semiconductor chip during a subsequent thermal cycle.

Abstract: A motion blurred image restoring method includes following steps. A blur parameter is estimated through a global motion relation between a target image and an image next to the target image, and a restored image is generated through the blur parameter. In order to avoid errors from occurring to the estimated blur parameter, the blue parameter is further adjusted according to the image quality value of the restored image, such that the restored image has a more desirable image quality.

Abstract: A combination assembly for an artificial anus has a spacer, a connecting panel and a mounting bracket. The spacer contacts with the skin of the human body and has a mounting hole formed through the spacer. The connecting panel is attached to the spacer and has a body. The body has a mounting hole, two mortises communicated with the mounting hole, and two mounting grooves communicated with the mortises. The mounting bracket is connected to the body and the spacer and has a mounting tube extended through the mounting holes in the connecting panel and the spacer and two tenons engaged with the mounting grooves respectively, and a bag is mounted around the mounting tube.

Abstract: A semiconductor package and a substrate structure thereof are provided. A solder mask layer applied on the substrate structure is formed with outwardly extended openings corresponding to corner portions of a chip mounting area of the substrate structure. When a flip-chip semiconductor chip is mounted on the chip mounting area and an underfilling process is performed, an underfill material can fill a gap between the flip-chip semiconductor chip and the substrate structure, and effectively fill the outwardly extended openings of the solder mask layer corresponding to the corner portions of the chip mounting area so as to provide sufficient protection for corners of the flip-chip semiconductor chip and prevent delamination at the corners of the flip-chip semiconductor chip during a subsequent thermal cycle.

Abstract: A three-axis adjustment ball pitching machine includes an azimuth adjustment device, an elevation adjustment device, a strut, an angle adjustment device and a pitching assembly. The azimuth adjustment device includes a base on which the elevation adjustment device is rotatably mounted. The elevation adjustment device includes a body rotatably mounted on the base and an elevation adjustment assembly. The elevation adjustment assembly includes a pivot seat pivotally mounted in the body, a transitional cylinder movably mounted in the pivot seat to pivot the pivot seat, and a threaded leading rod rotatably mounted in the body and held in the transitional cylinder. The strut is attached to pivot seat. The angle adjustment device includes a mounting housing rotatably mounted on the strut. The pitching assembly is attached to the mounting housing of the angle adjustment device. Consequently, the pitching machine can throw balls in various desired trajectories.