Patents by Inventor Wen-Hao Lin

Wen-Hao Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240404260
    Abstract: A distributed data processing system and a distributed data processing method are provided. The distributed data processing system includes a computing device and at least one additional computing device.
    Type: Application
    Filed: October 4, 2023
    Publication date: December 5, 2024
    Applicant: Acer Incorporated
    Inventors: Kai-Hsiang Lin, Hung-Chun Chou, Tung-Chan Tsai, Chieh-Sheng Wang, Shih-Hao Lin, Wen-Cheng Hsu
  • Publication number: 20240404258
    Abstract: Systems and methods are described for selecting models to perform monocular depth estimation. A computing device may receive a plurality of image and select an image from the plurality of images to evaluate a first machine-learning model and a plurality of machine-learning models are smaller than the first machine-learning model. The computing device may process the image using a first machine-learning model to generate a first predicted result. The computing device may also process the image using the plurality of machine-learning models to generate at least a second predicted result and a third test data set. The computing device may select a second machine-learning model from the plurality of machine-learning models based on a comparison of the first predicted result with the at least the second predicted result and the third test data set. The computing device may then process the plurality of images using the second machine-learning model.
    Type: Application
    Filed: May 30, 2023
    Publication date: December 5, 2024
    Inventors: Kai-Hsiang Lin, Hung-Chu Chou, Tung-Chan Tsai, Chieh-Sheng Wang, Shih-Hao Lin, Wen-Cheng Hsu
  • Publication number: 20240404259
    Abstract: A system and a method for presenting three-dimensional content and a three-dimensional content calculation apparatus are provided. In the method, the calculation apparatus receives a request for presentation content including one or more images from a client device, receives the presentation content from a content delivery network according to the request, processes the images using a first machine-learning model to generate a first predicted result, processes the images using multiple machine-learning models to generate at least a second predicted result and a third predicted result, selects a second machine-learning model from the machine-learning models based on a comparison of the first predicted result with the at least the second predicted result and the third predicted result, processes the images using the second machine-learning model and sends a processing result to the client device. Accordingly, the client device generates a three-dimensional presentation of the presentation content.
    Type: Application
    Filed: August 22, 2023
    Publication date: December 5, 2024
    Applicant: Acer Incorporated
    Inventors: Kai-Hsiang Lin, Hung-Chun Chou, Tung-Chan Tsai, Chieh-Sheng Wang, Shih-Hao Lin, Wen-Cheng Hsu
  • Patent number: 12159924
    Abstract: A method includes forming a fin that includes a first semiconductor layers and a second semiconductor layers alternatively disposed; forming a gate stack on the fin and a gate spacer disposed on a sidewall of the gate stack; etching the fin within a source/drain region, resulting in a source/drain trench; recessing the first semiconductor layers in the source/drain trench, resulting in first recesses underlying the gate spacer; forming inner spacers in the first recesses; recessing the second semiconductor layers in the source/drain trench, resulting in second recesses; and epitaxially growing a source/drain feature in the source/drain trench, wherein the epitaxially growing further includes a first epitaxial semiconductor layer extending into the second recesses; and a second epitaxial semiconductor layer on the first epitaxial semiconductor layer and filling in the source/drain trench, wherein the first and second epitaxial semiconductor layers are different in composition.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: December 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hsuan Chen, Wen-Chun Keng, Yu-Kuan Lin, Shih-Hao Lin
  • Publication number: 20240395902
    Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Chien-Chih Lin, Yen-Ting Chen, Wen-Kai Lin, Szu-Chi Yang, Shih-Hao Lin, Tsung-Hung Lee, Ming-Lung Cheng
  • Publication number: 20240387681
    Abstract: Semiconductor devices and methods of manufacture are presented in which spacers are manufactured on sidewalls of gates for semiconductor devices. In embodiments the spacers comprise a first seal, a second seal, and a contact etch stop layer, in which the first seal comprises a first shell along with a first bulk material, the second seal comprises a second shell along with a second bulk material, and the contact etch stop layer comprises a third bulk material and a second dielectric material.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu
  • Publication number: 20240386180
    Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su, Rabiul Islam, Shu-Yi Ying, Stefan Rusu, Kuan-Te Li, David Barry Scott
  • Publication number: 20240387433
    Abstract: A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 21, 2024
    Inventors: Po-Hao Tsai, Ming-Da Cheng, Wen-Hsiung Lu, Hsu-Lun Liu, Kai-Di Wu, Su-Fei Lin
  • Publication number: 20240387465
    Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes at least one first die, a plurality of bumps, a second die and a dielectric layer. The bumps are electrically connected to the at least one first die at a first side of the at least one first die. The second die is electrically connected to the at least one first die at a second side of the at least one first die. The second side is opposite to the first side of the at least one first die. The dielectric layer is disposed between the at least one first die and the second die and covers a sidewall of the at least one first die.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Hsu, Yung-Chi Lin, Wen-Chih Chiou
  • Patent number: 12140159
    Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.
    Type: Grant
    Filed: January 9, 2024
    Date of Patent: November 12, 2024
    Assignee: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Chun-Chieh Wang, Shu-Hao Kuo
  • Patent number: 12142668
    Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chih Lin, Yen-Ting Chen, Wen-Kai Lin, Szu-Chi Yang, Shih-Hao Lin, Tsung-Hung Lee, Ming-Lung Cheng
  • Patent number: 12135034
    Abstract: This disclosure relates to a thin pump including a case, a rotor, and a stator. The case has a bottom surface, a lower chamber, an upper chamber, and an accommodation space. The upper chamber is located further away from the bottom surface than the lower chamber. The upper chamber has two opposite ends respectively in fluid communication with the lower chamber and the accommodation space. The rotor includes an impeller and a magnet. The impeller is rotatably disposed in the lower chamber of the case. The magnet is disposed on the impeller. The stator is disposed in the case. The stator corresponds to the magnet of the rotor so as to drive the rotor to rotate with respect to the case.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: November 5, 2024
    Assignee: COOLER MASTER CO., LTD.
    Inventors: Chiu Yu Yeh, Wen-Hsien Lin, Wen-Hung Chen, Chia-Hao Sung
  • Publication number: 20240352584
    Abstract: The present disclosure generally provides an apparatus and method for gas diffuser support structure for a vacuum chamber. The gas diffuser support structure comprises a backing plate having a central bore, and a gas deflector having a length and a width unequal to the length coupled to the backing plate by a plurality of outward fasteners coupled to a plurality of outward threaded holes formed in the backing plate, in which a spacer is disposed between the backing plate and the gas deflector, and in which a length to width ratio of the gas deflector is about 0.1:1 to about 10:1.
    Type: Application
    Filed: March 27, 2024
    Publication date: October 24, 2024
    Inventors: Yu-Hsuan WU, Teng Mao WANG, Yan-Chi PAN, Yi-Jiun SHIU, Jrjyan Jerry CHEN, Cheng-yuan LIN, Hsiao-Ling YANG, Yu-Min WANG, Wen-Hao WU
  • Patent number: 12127441
    Abstract: Embodiments described herein relate to a device including a substrate, a plurality of adjacent pixel-defining layer (PDL) structures disposed over the substrate, and a plurality of sub-pixels. Each sub-pixel includes adjacent first overhangs, adjacent second overhangs, an anode, a hole injection layer (HIL) material, an additional organic light emitting diode (OLED) material, and a cathode. Each first overhang is defined by a body structure disposed on and extending laterally past a base structure disposed on the PDL structure. Each second overhang is defined by a top structure disposed on and extending laterally past the body structure. The HIL material is disposed over and in contact with the anode and disposed under the adjacent first overhangs. The additional OLED material is disposed on the HIL material and extends under the first overhang.
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: October 22, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Yu-hsin Lin, Ji Young Choung, Chung-chia Chen, Jungmin Lee, Wen-Hao Wu, Takashi Anjiki, Takuji Kato, Dieter Haas, Si Kyoung Kim, Stefan Keller
  • Patent number: 12120925
    Abstract: Embodiments described herein relate to a device comprising a substrate, a pixel-defining layer (PDL) structures disposed over the substrate and defining sub-pixels of the device, and a plurality overhang structures. Each overhang structure is defined by a top structure extending laterally past a body structure. Each body structure is disposed over an upper surface of each PDL structure. Overhang structures define a plurality of sub-pixels including a first sub-pixel and a second sub-pixel. Each sub-pixel includes an anode, an organic light-emitting diode (OLED) material, a cathode, and an encapsulation layer. The OLED materials are disposed over the first anode and extends under the overhang structures. The cathodes are disposed over the OLED materials and under the overhang structures. The encapsulation layers are disposed over the first cathode. The first encapsulation layer has a first thickness and the second encapsulation layer has a second thickness different from the first thickness.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: October 15, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Chung-chia Chen, Ji Young Choung, Dieter Haas, Yu-hsin Lin, Jungmin Lee, Wen-Hao Wu, Si Kyoung Kim
  • Publication number: 20240340598
    Abstract: A MEMS structure is provided. The MEMS structure includes a substrate having an opening portion and a backplate disposed on one side of the substrate. The backplate comprises a backplate conductive layer and a backplate insulating layer stacked with each other. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate and extending across the opening portion of the substrate. The MEMS structure further includes a pillar structure connected with the backplate. The pillar structure comprises a pillar conductive layer and a pillar insulating layer stacked with each other.
    Type: Application
    Filed: December 5, 2023
    Publication date: October 10, 2024
    Inventors: Chun-Kai MAO, Jien-Ming CHEN, Wen-Shan LIN, Nai-Hao KUO
  • Publication number: 20240339392
    Abstract: An electronic device includes a circuit structure including: a first insulation layer including a first opening; a second insulation layer disposed in the first opening and including a second opening; a conductive connection layer disposed in the second opening; and a first conductive layer and a second conductive layer respectively disposed on a surface and another surface of the first insulation layer. The first and the second conductive layer are electrically connected through the conductive connection layer, and the Young's modulus of the second insulation layer is less than the Young's modulus of the first insulation layer. In a cross-section of the electronic device, a center of the second opening and an outer surface of the second insulation layer are separated by a first distance X1, and a maximum width W of the second opening and the first distance X1 conform to the following formula: 1 . 5 ? W ? X 1 < 3 ? W .
    Type: Application
    Filed: March 8, 2024
    Publication date: October 10, 2024
    Inventors: Chih-Hao CHANG, Te-Hsun LIN, Wen-Hsiang LIAO
  • Publication number: 20240329139
    Abstract: Managing a battery including measuring, in response to a first charging current and over a first time period, a first amperage and a first voltage of the cell at predetermined intervals; measuring, in response to a second charging current and over a second time period, a second amperage and a second voltage of the cell at the predetermined intervals; determining that the first amperage of the cell was maintained greater than a first threshold amount of time within the first time period, and in response, qualifying the first amperage and the first voltage as stable; determining that the second amperage of the cell was maintained greater than a second threshold amount of time within the second time period, and in response, qualifying the second amperage and the second voltage as stable; and in response to the qualifying, calculating a DCIR of the cell based on the voltages and the amperage.
    Type: Application
    Filed: March 29, 2023
    Publication date: October 3, 2024
    Inventors: Jui Chin Fang, Chien-Hao Chiu, Wen-Yung Chang, Pei-Ying Lin
  • Patent number: 12096183
    Abstract: A MEMS structure is provided. The MEMS structure includes a substrate having an opening portion and a backplate disposed on one side of the substrate and having acoustic holes. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate and extending across the opening portion of the substrate. The diaphragm includes a ventilation hole, and an air gap is formed between the diaphragm and the backplate. The MEMS structure further includes a filler structure disposed on the diaphragm, and a portion of the filler structure is disposed in the ventilation hole.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: September 17, 2024
    Assignee: FORTEMEDIA, INC.
    Inventors: Chih-Yuan Chen, Feng-Chia Hsu, Chun-Kai Mao, Jien-Ming Chen, Wen-Shan Lin, Nai-Hao Kuo
  • Publication number: 20240302541
    Abstract: An electronic device, including a sensing substrate, a scintillator layer, and an adjustable reflective layer, is provided. The scintillator layer is disposed on the sensing substrate. The adjustable reflective layer is disposed on the sensing substrate and includes a first electrode, a second electrode, and an electrophoretic layer. The first electrode is disposed on the scintillator layer. The second electrode is disposed on the first electrode. The electrophoretic layer is disposed between the first electrode and the second electrode. The second electrode surrounds the scintillator layer.
    Type: Application
    Filed: February 1, 2024
    Publication date: September 12, 2024
    Applicant: InnoCare Optoelectronics Corporation
    Inventors: Chih-Hao Wu, Wen-Chien Lin