Abstract: The present invention is directed to semiconductor devices and manufacturing methods. According to an embodiment, the present invention provides a semiconductor have includes a circuit that is coupled to a substrate. The substrate comprises a plurality of layers, some of which comprise organic material. In some implementations, the substrate may be a coreless substrate that is free from a core material. There are other embodiments as well.

Abstract: An EM shielding structure for a semiconductor package is embedded in a through hole of a core layer of the semiconductor package. The EM shielding structure may include multiple vias formed by a copper plating operation. Additionally, a metal way surrounds the EM shielding structures and prevents, along with a dielectric material, unwanted EM radiation (passing through the vias) from emanating throughout the semiconductor package. The EM shielding structure can also take the form of an insert that is adhered to the core layer at a through hole of the core layer.

Abstract: A processor of a computer-aided design system reads and executes a software stored in a memory to input first digital data of a first component of the composite object, input second digital data of a second component of the composite object, analyze the first digital data and the second digital data with first criterion to obtain a plurality of first surfaces and a plurality of second surfaces respectively, calculate a distance between one of the plurality of the first surfaces and one of the plurality of the second surfaces, and output a first result when the distance is greater than or equal to the first threshold; otherwise, output a second result.

Abstract: One or more implementations of the subject technology may enable a bond-on-pad (BoP) substrate technology that can eliminate the need to utilize a solder-on-pad (SoP) process. Unlike an SoP process, a BoP Process does not require a solder bump to be formed on a bump pad to attach a joint to a bump pad. The size of an opening on a bump pad for a BoP process may be larger than that of an SoP process. A BoP process may use a solder mask having multiple thicknesses and may be thinner near the bump pads. A BoP process may use a joint having a copper pillar and a solder cap. A BoP process can be used with an underfill or a molding compound technology.

Abstract: A flexible substrate structure including a flexible substrate, a first dielectric layer, a metal-containing layer and a second dielectric layer is provided. The first dielectric layer is located on the flexible substrate. The metal-containing layer has a reflectivity greater than 15% and a heat transfer coefficient greater than 2 W/m-K. The metal-containing layer is disposed between the first dielectric layer and the second dielectric layer, and the second dielectric layer is an inorganic material layer. A flexible transistor including the above-mentioned flexible substrate structure and a method for fabricating the same are also provided.

Abstract: A shock-resistance testing apparatus includes a support base, a first rotating component and a controller provided on the support base. A second rotating component is coupled to one side of the first rotating component. A testing board is placed on the first rotating component. A falling board is placed on the testing board. The controller controls the first rotating component to drive the second rotating component rotating from one side of the testing board to another side of the testing board. The controller controls the second rotating component to lift the testing board. The controller controls the second rotating component to move away from the testing board so that the testing board falls.

Abstract: A flexible substrate structure including a flexible substrate, a first dielectric layer, a metal-containing layer and a second dielectric layer is provided. The first dielectric layer is located on the flexible substrate. The metal-containing layer has a reflectivity greater than 15% and a heat transfer coefficient greater than 2 W/m-K. The metal-containing layer is disposed between the first dielectric layer and the second dielectric layer, and the second dielectric layer is an inorganic material layer. A flexible transistor including the above-mentioned flexible substrate structure and a method for fabricating the same are also provided.

Abstract: A chipset with light energy harvester, includes a substrate, a functional element layer, and a light energy harvesting layer, both are stacked vertically on the substrate, and an interconnects connected between the functional element layer and the light energy harvesting layer.

Abstract: A test device for testing an electronic device has a base, a first mounting plane, a first support element, a plurality of second support elements, a plurality of test elements, and a control unit. The first mounting plane is mounted on the base. The first support element is slidable on the first mounting plane, the second support elements are slidable on the first support element, and the test elements are slidable on the second support elements. The control unit electrically coupled to the test elements controls the test elements to provide impact force on the electronic device.

Abstract: A shock-resistance testing apparatus includes a support base, a first rotating component and a controller provided on the support base. A second rotating component is coupled to one side of the first rotating component. A testing board is placed on the first rotating component. A falling board is placed on the testing board. The controller controls the first rotating component to drive the second rotating component rotating from one side of the testing board to another side of the testing board. The controller controls the second rotating component to lift the testing board. The controller controls the second rotating component to move away from the testing board so that the testing board falls.

Abstract: A chipset with light energy harvester, includes a substrate, a functional element layer, and a light energy harvesting layer, both are stacked vertically on the substrate, and an interconnects connected between the functional element layer and the light energy harvesting layer.

Abstract: A transistor device structure includes a substrate, a first polycrystalline semiconductor thin film and a first transistor unit. The first polycrystalline semiconductor thin film is disposed on the substrate. A grain diameter of the first polycrystalline semiconductor thin film is greater than 1 micrometer and a thickness of the first polycrystalline semiconductor thin film is less than three hundredths of the grain diameter. The first transistor unit is disposed on the first polycrystalline semiconductor thin film and includes a first gate dielectric layer and a first gate structure. The first gate dielectric layer is disposed on a surface of the first polycrystalline thin film semiconductor. The first gate structure is disposed on a surface of the first gate dielectric layer.

Abstract: A transistor device structure includes a substrate, a first transistor layer and a second transistor layer. The second transistor layer is disposed between the substrate and the first transistor layer. The first transistor layer includes an insulating structure and a first transistor unit. The insulating structure is disposed on the second transistor layer and has a protruding portion. The first transistor unit includes a gate structure, a source/drain structure, an embedded source/drain structure and a channel. The source/drain structure is disposed beside the gate structure and over the insulating structure. The embedded source/drain structure is disposed underneath the source/drain structure and in the insulating structure. The channel is defined between the protruding portion and the gate structure.

Abstract: A transistor device structure includes a substrate, a first polycrystalline semiconductor thin film and a first transistor unit. The first polycrystalline semiconductor thin film is disposed on the substrate. A grain diameter of the first polycrystalline semiconductor thin film is greater than 1 micrometer and a thickness of the first polycrystalline semiconductor thin film is less than three hundredths of the grain diameter. The first transistor unit is disposed on the first polycrystalline semiconductor thin film and includes a first gate dielectric layer and a first gate structure. The first gate dielectric layer is disposed on a surface of the first polycrystalline thin film semiconductor. The first gate structure is disposed on a surface of the first gate dielectric layer.

Abstract: The invention discloses a method for fabricating power-generating module with solar cell. The method includes the steps of providing a flexible substrate; forming a solar cell unit on the flexible substrate by using a high density plasma at a temperature lower than about 150° C.; and forming a circuit unit on the flexible substrate; wherein the solar cell unit is coupled to the circuit unit, so as to provide the power needed for the operation of the circuit unit.

Abstract: A ferroelectric memory device includes a memory layer, made of a silicon-based ferroelectric memory material. The silicon-based ferroelectric memory material includes a mesoporous silica film with nanopores and atomic polar structures on inner walls of the nanopores. The atomic polar structures are formed by asymmetrically bonding metal ions to silicon-oxygen atoms on the inner walls, and the silicon-based ferroelectric memory material includes semiconductor quantum dots, metal quantum dots and metal-semiconductor alloy quantum dots.

Abstract: A memory device comprises a substrate, a tunnel oxide layer, a charge trapping layer, a block oxide layer, a plurality of conductive quantum dots, a metal gate and a source/drain structure. The tunnel oxide layer is disposed on the substrate and has a thickness substantially less than or equal to 2 nm. The charge trapping layer is disposed on the tunnel oxide layer. The quantum dots are embedded in the charge trapping layer. The block oxide layer is disposed on the charge trapping layer. The metal gate essentially consisting of aluminum (Al), copper (Cu), tantalum nitride (TiN), titanium nitride (TaN), aluminum-silicon-copper (Al—Si—Cu) alloys or the arbitrary combinations thereof is disposed on the block oxide layer. The source/drain structure is disposed in the substrate.

Abstract: The invention discloses a method for fabricating power-generating module with solar cell. The method includes the steps of providing a flexible substrate; forming a solar cell unit on the flexible substrate by using a high density plasma at a temperature lower than about 150° C.; and forming a circuit unit on the flexible substrate; wherein the solar cell unit is coupled to the circuit unit, so as to provide the power needed for the operation of the circuit unit.

Abstract: The invention discloses a power-generating module with solar cell and method for fabricating the same. The power-generating module includes a flexible substrate, a circuit and a solar cell. Both of the circuit and the solar cell are formed on the flexible substrate and are connected with each other, such that the solar cell is capable of providing the power needed by the circuit for operation.

Abstract: A light-trapping layer is integrated into a thin-film solar cell. It is integrated as a light-inlet layer, an intermediate layer or a shaded layer with nano-particles embedded in a transparent or non-transparent conductive film. Thus, light stays longer in an absorption layer with photocurrent increased; defects of interface between the absorption layer and the nano-material are decreased; anti-reflective effect to inlet light is enhanced; and a good integrity and a good reliability for long-time light-shining are obtained.