Abstract: A method for fabricating a semiconductor package includes applying polymer-based solder paste onto a substrate; bringing a plurality of solder bumps on a semiconductor die into contact with the polymer-based solder paste on the substrate; reflowing the polymer-based solder paste to form a plurality of solder joints between the substrate and the semiconductor die, wherein a post-soldering residue is produced to encapsulate a lower portion of each solder joint; and applying an underfill between the substrate and the semiconductor die to encapsulate an upper portion of the solder joint.

Abstract: A page buffer circuit adapted for a page-read device which including a memory array having several pages and several bit lines. The page buffer circuit comprises the following elements. First latches, receive a weight-vector from a corresponding one of the pages through the bit lines, and import an input-vector through a data input/output path. The weight-vector has a plurality of weight bit-data, and the input-vector has a plurality of input bit-data. Second latches, store the input bit-data of the input-vector. Logic operation units, coupled to the first latches to receive the weight bit-data, and coupled to the second latches to receive the input bit-data, perform a logic operation of the input bit-data and the weight bit-data to generate a logic operation result. The logic operation result is sent to one the first latches. A control circuit, selectively enables the logic operation units to perform the logic operation.

Abstract: A filtered search method, for performing a search within a data set, and the data set includes several data points. The filtered search method includes the following steps. Dividing the data set into several clusters based on a similarity of the data points. Dividing each of the clusters into an inlier part and an outlier part based on a distribution density of the data points. Performing a coarse search on all of the inlier parts, to filter out inlier parts of a first candidate number. Performing a fine search on the inlier parts of the first candidate number, to search data points of a second candidate number. Obtaining a search result based on the data points of the second candidate number, and the data points of the second candidate number are close to a target point.

Abstract: The disclosure discloses a memory device and an operation method thereof. A target memory cell and at least one replicated memory cell belonging to the same memory string are selected. A target weight value written into the target memory cell is replicated to the at least one replicated memory cell, wherein the target memory cell and the at least one replicated memory cell store the target weight value. In response to a command of reading or computing on the target memory cell received by the memory device, reading or computing is performed on the target memory cell and the at least one replicated memory cell simultaneously.

Abstract: A filtered search method, for performing a search within a data set, and the data set includes several data points. The filtered search method includes the following steps. Dividing the data set into several clusters based on a similarity of the data points. Dividing each of the clusters into an inlier part and an outlier part based on a distribution density of the data points. Performing a coarse search on all of the inlier parts, to filter out inlier parts of a first candidate number. Performing a fine search on the inlier parts of the first candidate number, to search data points of a second candidate number. Obtaining a search result based on the data points of the second candidate number, and the data points of the second candidate number are close to a target point.

Abstract: An analog-to-digital conversion device, includes the following elements. A sensing circuit, coupled to a bit line of a memory array, and used to sense a current in the bit line to generate a bit-sequence, the bit-sequence has a form of a thermometer code to represent an analog value. A latch logic circuit, including a plurality of latches and a plurality of logic circuits to form a page buffer of the memory array, and used to generate a bit-set according to the bit-sequence, the bit-set has a form of a binary code to represent a digital value. The latches and the logic circuits are used to perform a conversion process to convert the bit-sequence into the bit-set, and the conversion process has a bit width.

Abstract: The application discloses a memory device and a computation method thereof. A plurality of weight data are stored in a plurality of first memory cells of the memory device. A plurality of input data are input via a plurality of string select lines. A plurality of memory cell currents are generated in the plurality of first memory cells based on the weight data and the input data. The memory cell currents are summed on a plurality of bit lines coupled to the plurality of string select lines to obtain a plurality of summed currents. The summed currents are converted into a plurality of analog-to-digital conversion results. The plurality of analog-to-digital conversion results are accumulated to obtain a computational result.

Abstract: The present disclosure relates generally to topical delivery compositions for improved topical composition comprising at least one active agent, at least one phospholipid and urea. The active agent of the present disclosure comprises non-steroid anti-inflammatory drugs (NSAIDs). The topical delivery compositions of the present disclosure improve the solubility of the NSAIDs. The present disclosure also relates to a method for preparation of a topical composition of the present disclosure. The topical compositions are useful in treating inflammation, arthritis and/or pain, or conditions for which the signs and symptoms include inflammation, arthritis and/or pain, by topical administration to a subject.

Abstract: A lens module including an integrated lens holder and a lens group is provided. The lens holder is composed of a fixed piece and a lens frame. The lens frame is connected to the fixed piece. The lens frame includes an accommodating cavity and a bearing surface located in a periphery of the accommodating cavity. The lens group is disposed in the accommodation cavity and is supported on the bearing surface.

Abstract: Provided is a catenated VAR2CSA recombinant protein, a preparation therefor and a use thereof. The catenated VAR2CSA recombinant protein comprises a binding domain, SpyTag, a p53dim structural domain, and SpyCatcher, which are randomly arranged. The binding domain comprises a structural domain, in the VAR2CSA protein, binding to placenta-like chondroitin sulfate A. The catenated VAR2CSA recombinant protein has high stability and affinity to the tumor-specific antigen placenta-like chondroitin sulfate A, and can be effectively used in the field of tumor immunotherapy, such as immune cell therapy.

Abstract: A hard disk, a fixing device, and a hard disk module are provided. The hard disk includes a base shell, a main circuit board mounted on the base shell, a switch mounted on the main circuit board, and a triggering mechanism. The triggering mechanism includes a triggering rod. The triggering rod is slidably arranged on the base shell along a first direction.

Abstract: Disclosed is a vehicle control method, including: obtaining a first velocity planned for an intelligent vehicle to travel in a first area; and obtaining a second velocity planned for the vehicle to travel in the first area, where the second velocity is obtained based on a collision potential energy, the first velocity and the second velocity each include a direction and a magnitude, and the first velocity, the second velocity, and a risk of a collision between the vehicle and a surrounding obstacle are used to determine an optimal velocity of the vehicle, so that the vehicle can effectively avoid the obstacle, thereby improving traveling safety of the vehicle. Also disclosed are a vehicle control apparatus, a vehicle controller, and a vehicle.

Abstract: Provided are a chimeric antigen receptor and an application thereof; said chimeric antigen receptor contains a domain which identifies any one of, or a combination of at least two of, the malarial protein VAR2CSA, a protein tag on malarial protein VAR2CSA, or a compound capable of labeling the malarial protein VAR2CSA. The chimeric antigen receptor can identify the VAR2CSA protein or the recombinant protein (rVAR2) of any one of, or at least two of, the domains of the VAR2CSA protein which can bind to placental-like chondroitin sulfate A (pl-CSA). The VAR2CSA protein or rVAS2 protein is capable of targeting several different types of tumor cells by means of binding to the pl-CSA on the surface of the tumor cell.

Abstract: A structure for mounting a storage device to a server and providing a fast installation and removal of a storage device includes a carrier and a chassis. The carrier includes a rotatable handle with a cam on the axis of rotation and a frame. The cam is connected to the frame. The chassis includes an immovable limiting component. With the carrier mounted in the chassis, rotation of the handle clockwise or counterclockwise pushes the carrier to move, to lock or unlock the carrier because of the limiting component resting against the cam. The structure greatly improves the convenience of the installation and removal of the storage device. A computing device is also disclosed.

Abstract: A graphics processing unit (GPU) tray includes a base, a first riser, and a second riser. The base is provided with a first bracket and a second bracket spaced from each other, the first riser is connected to one side of the first bracket and the second bracket, and the second riser is connected to the other side of the first bracket and a second bracket. The first riser is provided with a first connector socket facing the second riser, and the second riser is provided with a second connector socket facing the first riser. A first GPU is plugged to the first connector socket and a second GPU is plugged to the second connector socket. The GPU tray compress the installation space of the GPUs and allows four GPUs can be installed in the chassis. A chassis accommodating the GPU tray is also disclosed.

Abstract: A retention assembly for positioning a mounting component slidably arranged on a frame, the retention assembly includes a detent cylinder defining a receiving hole therethrough, a cap covering the receiving hole, and a retention ball and an elastic member located in the receiving hole, the elastic member is arranged between the retention ball and the cap for pressing the retention ball to protrude from the receiving hole and insert into a positioning hole of the mounting component when the positioning hole is aligned with the retention ball. The retention assembly improves convenience of positioning the mounting component relative to the frame and the convenience of maintenance on the electronic components mounted on the mounting component. A chassis including the retention assembly is also provided.

Abstract: Disclosed is a control method for a hybrid parallel integrated power supply. Under the condition of a 2:1 current ratio between a Si-based inverter and a SiC-based inverter, an optimal power ratio between the two inverters is obtained by reducing a power loss of a fundamental wave component on the Si-based inverter. Based on the fitting for effective values of a harmonic current on the Si-based inverter, an optimal switching frequency of the Si-based inverter and a relationship between a minimum harmonic-current conduction loss and a switching loss under the optimal switching frequency are obtained. Zero sequence components of the current are eliminated through rapid switching of the SiC-based inverter, to suppress harmonic waves.

Abstract: The present disclosure provides an optimal current selection method for a hybrid parallel integrated power supply, including the following steps: selecting multiple power device combinations with different current ratios, the combinations being formed by silicon insulated-gate bipolar transistor (Si IGBT) and silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) devices; comparing cost and junction temperatures on the Si IGBT devices and the SiC MOSFET devices under the different current ratios; comparing efficiency of a hybrid parallel integrated power supply with the different current ratios under different SiC MOSFET switching frequencies; comparing electromagnetic interference (EMI) noise of the hybrid parallel integrated power supply; selecting an optimal current ratio for the hybrid parallel integrated power supply.

Abstract: An in-memory computing method and an in-memory computing apparatus are adapted to perform multiply-accumulate (MAC) operations on a memory by a processor. In the method, a pre-processing operation is respectively performed on input data and weight data to be written into input lines and memory cells of the memory to divide the input data and weight data into a primary portion and a secondary portion. The input data and the weight data divided into the primary portion and the secondary portion are written into the input lines and the memory cells in batches to perform the MAC operations and obtain a plurality of computation results. According to a numeric value of each of the computation results, the computation results are filtered. According to the portions to which the computation results correspond, a post-processing operation is performed on the filtered computation results to obtain output data.