Abstract: An electronic device includes a chassis. The chassis has a bottom wall and a rear wall, substantially perpendicular to the bottom wall. A motherboard is disposed on the bottom wall, and a riser card is perpendicularly connected to the motherboard. An expansion card is substantially parallel to the motherboard and coupled to the riser card. The expansion card has a first end and a second end, and the first end is secured to the rear wall. An airflow duct is located on the bottom wall of the chassis. A supporting bar protrudes from the airflow duct. A securing member is pivotably mounted to the airflow duct. The securing member includes a pressing plate. The second end of the expansion card is clamped between the pressing plate and the supporting bar of the airflow duct.

Abstract: A mounting apparatus for a PCI card includes a mounting bracket, a securing piece adapted to attach the PCI card to the mounting bracket and a securing member. The mounting bracket has a base and a blocking plate perpendicular to the base. The securing member includes a pressing piece and a securing piece rotatably attached to the pressing piece. The mounting piece includes a mounting end. The securing piece includes a securing portion. The securing piece is capable of engaging with an inside surface of the mounting bracket by rotating the securing piece relative to the pressing piece, thereby sandwiching the mounting end of the securing piece between the blocking plate and the pressing piece.

Abstract: An electronic device includes a chassis having a bottom wall. A motherboard is disposed on the bottom wall. A riser card is perpendicularly connected to the motherboard. An airflow duct is located on the bottom wall of the chassis. A securing member is mounted to the airflow duct. The securing member includes a supporting piece secured to the airflow duct, and a securing piece is pivotally mounted to the supporting piece. The securing piece is engaged with the supporting piece to clamp an expansion card between the supporting piece and the securing piece.

Abstract: An electronic device includes a chassis, a motherboard, an airflow duct, and an expansion card. The chassis includes a bottom wall, a rear wall, and a sidewall. A motherboard is disposed on the bottom wall, and a riser card perpendicularly connected to the motherboard. An expansion card is parallel to the motherboard and inserted in the riser card. The expansion card has a first end and a second end. The first end is secured to the rear wall of the chassis. An airflow duct is located on the bottom wall of the chassis. The airflow duct includes a mounting wall parallel to the chassis rear wall. The first end of the expansion card is secured to the rear wall, and the second end of the expansion card is mounted to the mounting wall of the airflow duct.

Abstract: An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

Abstract: An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

Abstract: In a file transfer security system and method, a file transfer request sent to a file server is intercepted. The need for examination of the file transfer request is assessed, and, if present, an auditor is notified to examine the file transfer request and award approval or rejection thereof. File operations are executed according to the examination result.

Abstract: A non-volatile memory cell has a substrate layer with a fin shaped semiconductor member of a first conductivity type on the substrate layer. The fin shaped member has a first region of a second conductivity type and a second region of the second conductivity type, spaced apart from the first region with a channel region extending between the first region and the second region. The fin shaped member has a top surface and two side surfaces between the first region and the second region. A word line is adjacent to the first region and is capacitively coupled to the top surface and the two side surfaces of a first portion of the channel region. A floating gate is adjacent to the word line and is insulated from the top surface and is capacitively coupled to the two side surfaces of a second portion of the channel region. A coupling gate is capacitively coupled to the floating gate. An erase gate is insulated from the second region and is adjacent to the floating gate and coupling gate.

Abstract: An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

Abstract: A superhydrophilic thin film is formed on a metal surface of a boiler vessel to alter the wettability and roughness of the surface, which, in turn, changes the boiling behavior at the surface. The superhydrophilic film is formed by depositing a layer of a first ionic species on the surface from a solution. A second ionic species having a charge opposite to the that of the first ionic species is then deposited from solution onto the surface to produce a bilayer of the first ionic species and the oppositely charged second ionic species. The depositions are then repeated to form a plurality of bilayers, on top of the preceding bilayer. The bilayers are then heated, leaving the second ionic species on the metal surface to form a superhydrophilic film.

Abstract: A method for in-situ treatment of a metallic surface utilizing a nanoparticle dispersion to increase at least one of (i) the critical heat flux. (ii) the boiling heat transfer rate, or (iii) the corrosion resistance of the metallic surface when in operation without a nanofluid heat transfer liquid, comprising: (1) cleaning the metallic surface: (2) conditioning the metallic surface to enhance nanoparticle binding to the metallic surface by applying a polymeric binding agent; (3) forming at least one thin film layer of nanoparticles on the metallic surface by contacting the nanoparticle dispersion with the metallic surface at a temperature and pressure sufficient to boil the nanoparticle dispersion; and, optionally (4) curing the nanoparticle layer by heating the metallic surface to a temperature higher than the temperature sufficient to boil the nanoparticle dispersion.

Abstract: A heat pipe includes a longitudinal casing, a main wick structure, at least one auxiliary wick structure and a working fluid contained in the casing and saturating the main wick structure and the at least one auxiliary wick structure. The main wick structure is received in the casing and attached to an inner surface of the casing. The at least one auxiliary wick structure is received in the main wick structure. An inner peripheral surface of the main wick structure and an outer peripheral surface of the at least one auxiliary wick structure cooperatively define a vapor channel therebetween. At least one end of the at least one auxiliary wick structure is fixed on a corresponding end of the casing.

Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”).

Abstract: A mixer circuit is provided. The mixer circuit comprises: a voltage-to-current converter stage; a switching stage comprising a plurality of switches, the switching stage being coupled with the voltage-to-current converter stage to controlled passing electrical current from the voltage-to-current converter stage through the switches; and a frequency conversion stage coupled to the switching stage. A mixer circuit arrangement is also provided.

Abstract: The invention relates to an orthogonal frequency division multiplexing system with PN-sequence. In the synchronization of the invention, both timing offset and frequency offset are estimated and compensated by utilizing a time and frequency synchronization device. In addition, the PN-sequence with the cyclic prefix is added to the OFDM symbol before transmitting. The time and frequency synchronization device of the invention comprises two synchronization circuits from the cyclic prefix and PN-sequence when calculating the timing offset and frequency offset of receiving signal. As a result, the OFDM system of the invention not only has better performance in fading channel, but also has the better bandwidth utilization without extra bandwidth for transmitting the PN-sequence.

Abstract: An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”).

Abstract: A first embodiment of an Electrostatic Discharge (ESD) structure for an integrated circuit for protecting the integrated circuit from an ESD signal, has a substrate of a first conductivity type. The substrate has a top surface. A first region of a second conductivity type is near the top surface and receives the ESD signal. A second region of the second conductivity type is in the substrate, separated and spaced apart from the first region in a substantially vertical direction. A third region of the first conductivity type, heavier in concentration than the substrate, is immediately adjacent to and in contact with the second region, substantially beneath the second region. In a second embodiment, a well of a second conductivity type is provided in the substrate of the first conductivity type. The well has a top surface. A first region of the second conductivity type is near the top surface. A second region of the second conductivity type is in the well, substantially along the bottom of the well.

Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”).

Abstract: A method of detecting, characterizing and treating viral infection is provided. In particular, a strategy of molecular mimicry is provided for characterizing viral behavior and/or a predisposition for a given viral outcome in vivo. Novel compositions are also provided for detecting, characterizing and treating viral infections.