Patents by Inventor Wen Huang

Wen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230383138
    Abstract: A manufacturing method of an elastic paint is provided. The manufacturing method includes: blending an original composition to produce a first rough painting material, where the original composition includes polycarbonatediol (PCDL), a polyurethane (PU) elastic powder, poly(methyl methacrylate) (PMMA), a photoinitiator, a wetting agent, a solvent, and an auxiliary agent; carrying out precipitation treatment on the first rough painting material, and filtering the treated first rough painting material, to produce a second rough painting material; blending the second rough painting material; sealing the blended second rough painting material to produce a plurality of layers in the second rough painting material; removing an upper portion and a lower portion from the layers to produce a main ingredient; and adding a curing agent and a diluent into the main ingredient to produce an elastic paint.
    Type: Application
    Filed: December 6, 2022
    Publication date: November 30, 2023
    Inventors: Guo Lin YANG, Po-Wen HUANG, Yu-Chun YANG
  • Publication number: 20230388546
    Abstract: Video encoding methods and apparatuses in a video encoding system receive an input residual signal of a current block by a shared transform circuit, apply horizontal transform and vertical transform by a shared transform circuit to generate transform coefficients, apply quantization and inverse quantization to generate recovered transform coefficients, apply inverse vertical transform and inverse horizontal transform to the recovered transform coefficients by the shared transform circuit to generate a reconstructed residual signal for the current block, and encode the current block based on quantized levels of the current block. The shared transform circuit and a coefficient buffer in the folded 4-time transform architecture reuse computation resources in each transform stage. In some embodiments of the folded 4-time transform architecture, a hierarchical design for block size grouping is implemented with fixed throughput for uniform hardware scheduling.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Inventors: Chih-Hsuan LO, Man-Shu CHIANG, Chun-Chia CHEN, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Patent number: 11832438
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: November 28, 2023
    Assignee: Intel Corporation
    Inventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Jared Stoeger, Yu-Wen Huang, Shu Zhou
  • Publication number: 20230378058
    Abstract: Semiconductor packages and methods of forming the same are disclosed. An semiconductor package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.
    Type: Application
    Filed: August 1, 2023
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Publication number: 20230369501
    Abstract: Techniques are provided herein for forming transistor devices with reduced parasitic capacitance, such as transistors used in a memory structure. In an example, a given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT), and the storage device may include a capacitor. Any of the given TFTs may include a dielectric liner extending along sidewalls of the TFT. The TFT includes a recess (e.g., a dimple) that extends laterally inwards toward a midpoint of a semiconductor region of the TFT. The dielectric liner thus also pinches or otherwise extends inward. This pinched-in dielectric liner may reduce parasitic capacitance between the contacts of the TFT and the gate electrode of the TFT. The pinched-in dielectric liner may also protect the contacts from forming too deep into the semiconductor region.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Applicant: Intel Corporation
    Inventors: Cheng Tan, Yu-Wen Huang, Hui-Min Chuang, Xiaojun Weng, Nikhil J. Mehta, Allen B. Gardiner, Shu Zhou, Timothy Jen, Abhishek Anil Sharma, Van H. Le, Travis W. Lajoie, Bernhard Sell
  • Publication number: 20230369540
    Abstract: A semiconductor stack includes a first-type semiconductor layer, a second-type semiconductor layer, an active region located between the first-type semiconductor layer and the second-type semiconductor layer, one or multiple recesses, and a recess-induced layer located between the first-type semiconductor layer and the active region. The active region has a first thickness and includes an upper surface and a lower surface closer to the first-type semiconductor layer than the upper surface. Each recess includes a bottom disposed in the active region. A first distance is from the bottom of the recess to the lower surface. The first distance is 0.5-0.9 times the first thickness.
    Type: Application
    Filed: May 11, 2023
    Publication date: November 16, 2023
    Inventor: Feng-Wen HUANG
  • Publication number: 20230369092
    Abstract: Some implementations described herein provide techniques and apparatuses for a semiconductor processing tool including an electrostatic chuck having a voltage-regulation system to regulate an electrical potential throughout regions of a semiconductor substrate positioned above the electrostatic chuck. The voltage-regulation system may determine that an electrical potential within a region of the semiconductor substrate does not satisfy a threshold. The voltage-regulation system may, based on determining that the electrical potential throughout the region does not satisfy the threshold, position one or more electrically-conductive pins within the region. While positioned within the region, the one or more electrically-conductive pins may change the electrical potential of the region.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Chung-Pin CHOU, Kai-Lin CHUANG, Sheng-Wen HUANG, Yan-Cheng CHEN, Jun Xiu LIU
  • Patent number: 11818097
    Abstract: A method and system for mitigating a threat associated with network data packets are provided. The method commences with receiving, by an authentication server, a request for access to a server from a client. The method further includes authenticating the client by the authentication server. The authentication includes providing an authentication token to the client. The method continues with receiving, by a mitigation device, from the client, at least one network packet directed to the server. The at least one network packet embeds the authentication token. The method further includes validating, by the mitigation device, authenticity of the authentication token and selectively forwarding, based on the validation, the at least one network packet to the server. The authentication token is independently generated by the authentication server, the mitigation device, and the server using a shared token generation algorithm based on a hash salt value.
    Type: Grant
    Filed: April 25, 2021
    Date of Patent: November 14, 2023
    Inventors: Yutun (Tony) Tseng, Ahmed Abdelhalim, Vernon Richard Groves, Ching-Wen Huang
  • Publication number: 20230362403
    Abstract: Video encoding or decoding methods and apparatuses include receiving input data associated with a current block in a current picture, determining a preload region in a reference picture shared by two or more coding configurations of affine prediction or motion compensation or by two or more affine refinement iterations, loading reference samples in the preload region, generating predictors for the current block, and encoding or decoding the current block according to the predictors. The predictors associated with the affine refinement iterations or coding configurations are generated based on some of the reference samples in the preload region.
    Type: Application
    Filed: May 4, 2022
    Publication date: November 9, 2023
    Inventors: Chih-Hsuan LO, Tzu-Der CHUANG, Ching-Yeh CHEN, Chun-Chia CHEN, Chih-Wei HSU, Yu-Wen HUANG
  • Publication number: 20230349001
    Abstract: A biomolecular characteristic identification method includes: breeding a plurality of Taiwan Tilapias in a predetermined environment to obtain a plurality of baited Taiwan Tilapias; seeking at least one nucleotide mark in the baited Taiwan Tilapias to obtain at least one feature sequence marker therefrom; producing at least one design of primer pair according to the feature sequence marker for identification; and identifying an unknown DNA sample of the baited Taiwan Tilapias with the at least one primer pair in a biomolecular tracing procedure to obtain an identification result.
    Type: Application
    Filed: June 23, 2022
    Publication date: November 2, 2023
    Inventors: CHANG-WEN HUANG, TE-HUA HSU, HONG-YI GONG
  • Publication number: 20230349005
    Abstract: An exogenous biomolecular tracing method includes: extracting a nucleotide marker from a marker source organism; combining a basic material with the nucleotide marker to form a nucleotide marked material; exogenously combining an aquatic creature or an aquatic product to form an exogenously-marked aquatic creature or an exogenously-marked aquatic product; and identifying a DNA sample from the exogenously-marked aquatic creature or the exogenously-marked aquatic product with at least one primer pair in an exogenous biomolecular tracing procedure to obtain an exogenously-marked identification result.
    Type: Application
    Filed: June 23, 2022
    Publication date: November 2, 2023
    Inventors: TE-HUA HSU, HUNG-TAI LEE, HONG-YI GONG, CHANG-WEN HUANG
  • Patent number: 11803112
    Abstract: A projection device and its display method are provided. The projection device includes a light source module, a control device, a light valve module, and a lens module. The light source module provides an illumination beam and includes first and second light sources respectively emitting first and second sub-color beams and a driving circuit driving the first and second light sources. The illumination beam includes the first and second sub-color beams. The light valve module converts the illumination beam to an image beam. The lens module projects the image beam. The projection device is configured to have multiple color gamut modes. In at least partial time of a first time slot, the control device controls the driving circuit to simultaneously drive the first and second light sources.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: October 31, 2023
    Assignee: Coretronic Corporation
    Inventor: Chin-Wen Huang
  • Patent number: 11805245
    Abstract: For each prediction candidate of a set of one or more prediction candidates of the current block, a video coder computes a matching cost between a set of reference pixels of the prediction candidate in a reference picture and a set of neighboring pixels of a current block in a current picture. The video coder identifies a subset of the reference pictures as major reference pictures based on a distribution of the prediction candidates among the reference pictures of the current picture. A bounding block is defined for each major reference picture, the bounding block encompassing at least portions of multiple sets of reference pixels for multiple prediction candidates. The video coder assigns an index to each prediction candidate based on the computed matching cost of the set of prediction candidates. A selection of a prediction candidate is signaled by using the assigned index of the selected prediction candidate.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: October 31, 2023
    Inventors: Chih-Yao Chiu, Chun-Chia Chen, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Publication number: 20230341765
    Abstract: A method includes: providing a first design layout including a plurality of cells; updating a first cell of the plurality of cells using optical proximity correction to provide a first updated cell and a data set; and updating a second cell from remaining cells in the first design layout based on the data set and a model without involvement of optical proximity correction to provide a second updated cell, wherein the model includes hidden layers including nodes and is trained to obtaining converged values of the nodes of the hidden layers through providing a mapping of edge segments before lithography enhancement and edge segments after lithography enhancement using optical proximity correction, and wherein at least one of the providing, and updating is executed by one or more processors.
    Type: Application
    Filed: June 29, 2023
    Publication date: October 26, 2023
    Inventors: WEI-LIN CHU, HSIN-LUN TSENG, SHENG-WEN HUANG, CHIH-CHUNG HUANG, CHI-MING TSAI
  • Publication number: 20230345029
    Abstract: Method and apparatus for affine CPMV or ALF refinement are mentioned. According to this method, statistical data associated with the affine CPMV or ALF refinement are collected over a picture area. Updated parameters for the affine CPMV refinement or the ALF refinement are then derived based on the statistical data, where a process to derive the updated parameters includes performing multiplication using a reduced-precision multiplier for the statistical data. The reduced-precision multiplier truncates at least one bit of the mantissa part. In another embodiment, the process to derive the updated parameters includes performing reciprocal for the statistical data using a lookup table with (m?k)-bit input by truncating k bits from the m-bit mantissa part, and contents of the lookup table includes m-bit outputs. m and k are positive integers.
    Type: Application
    Filed: April 25, 2022
    Publication date: October 26, 2023
    Inventors: Shih-Chun CHIU, Tzu-Der CHUANG, Ching-Yeh CHEN, Chun-Chia CHEN, Chih-Wei HSU, Yu-Wen HUANG
  • Publication number: 20230343885
    Abstract: Image sensors and methods of forming the same are provided. An image sensor according to the present disclosure includes a silicon substrate, a germanium region disposed in the silicon substrate, a doped semiconductor isolation layer disposed between the silicon substrate and the germanium region, a heavily p-doped region disposed on the germanium region, a heavily n-doped region disposed on the silicon substrate, a first n-type well disposed immediately below the germanium region, a second n-type well disposed immediately below the heavily n-doped region, and a deep n-type well disposed below and in contact with the first n-type well and the second n-type well.
    Type: Application
    Filed: June 8, 2022
    Publication date: October 26, 2023
    Inventors: Hsiang-Lin Chen, Sin-Yi Jiang, Sung-Wen Huang Chen, Yin-Kai Liao, Jung-I Lin, Yi-Shin Chu, Kuan-Chieh Huang
  • Patent number: 11800102
    Abstract: Low-latency video coding methods and apparatuses include receiving input data associated with a current Intra slice composed of Coding Tree Units (CTU), where each CTU includes luma and chroma Coding Tree Blocks (CTBs), partitioning each CTB into non-overlapping pipeline units, and encoding or decoding the CTUs in the current Intra slices by performing processing of chroma pipeline units after beginning processing of luma pipeline units in at least one pipeline stage. Each of the pipeline units is processed by one pipeline stage after another pipeline stage, and different pipeline stages process different pipeline units simultaneously. The pipeline stage in the low-latency video coding methods and apparatuses simultaneously processes one luma pipeline unit and at least one previous chroma pipeline unit within one pipeline unit time interval.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: October 24, 2023
    Assignee: MEDIATEK INC.
    Inventors: Chia-Ming Tsai, Chun-Chia Chen, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Publication number: 20230329669
    Abstract: A system for visualization and quantification of ultrasound imaging data may include a display unit, and a processor communicatively coupled to the display unit and to an ultrasound imaging apparatus for generating an image from ultrasound data representative of a bodily structure and fluid flowing within the bodily structure. The processor may be configured to generate vector field data corresponding to the fluid flow, wherein the vector field data comprises axial and lateral velocity components of the fluid, extract spatiotemporal information from the vector field data at one or more user-selected points within the image, and cause the display unit to concurrently display the spatiotemporal information at the one or more user-selected points with the image including a graphical representation of the vector field data overlaid on the image, wherein the spatiotemporal information includes at least one of a magnitude and an angle of the fluid flow.
    Type: Application
    Filed: June 1, 2023
    Publication date: October 19, 2023
    Inventors: Shiying Wang, Sheng-Wen Huang, Hua Xie, Francois Guy Gerard Marie Vignon, Liang Zhang, Keith William Johnson
  • Patent number: 11792394
    Abstract: According to a method for Adaptive Loop Filter (ALF) processing of reconstructed video, multiple indicators are signaled in slice at an encoder side or parsed at a decoder side, where the multiple indicators are Adaptive Parameter Set (APS) indices associated with temporal ALF filter sets for the ALF processing. A current indicator is determined from the multiple indicators, where the current indicator is used to select a current ALF filter set. Filtered-reconstructed pixels are derived for the current block by applying the current ALF filter to the current block. In another method, if the ALF processing applied at a target sample requires an outside sample on other side of a target virtual boundary from the target sample, the outside sample is replaced by a padded sample.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: October 17, 2023
    Assignee: HFI INNOVATION INC.
    Inventors: Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Publication number: 20230328256
    Abstract: Methods and apparatus for video coding system utilizing Rate-Distortion Optimized Quantization (RDOQ) are provided. According to one method, a rate for a level belonging to a level set of a current quantized transform coefficient is estimated for a current coefficient group (CG) based on neighboring quantized coefficients of the current quantized transform coefficient and the current CG. A best level for the current quantized transform coefficient is selected from the level set for a best RD-cost. In another method, a TB is partitioned into M regions and M best regions are derived for the M regions according to RDOQ. At least two alternative region RD-costs are generated for each of the M best regions based on a relative position between each of the M best regions and a last significant region in the TB. TB RD-cost for the TB is selected according a last non-zero best region position.
    Type: Application
    Filed: April 6, 2022
    Publication date: October 12, 2023
    Inventors: Chen-Yen LAI, Tzu-Der CHUANG, Ching-Yeh CHEN, Chun-Chia CHEN, Chih-Wei HSU, Yu-Wen HUANG