Patents by Inventor Wen Huang

Wen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240016373
    Abstract: A capsule endoscope, an endoscope system, and an image correction method are provided. The capsule endoscope includes an image sensor and a posture sensor. The image sensor is coupled to a processor and obtains a sensed image. The posture sensor is coupled to the processor and obtains three-axis data. The processor calculates a screen rotation angle according to the three-axis data and corrects the sensed image according to the screen rotation angle. A first axis and a second axis of the corrected sensed image rotate toward an actual vertical axis and an actual horizontal axis.
    Type: Application
    Filed: July 13, 2023
    Publication date: January 18, 2024
    Applicant: Pro-Sight Medical Technology CORP.,LTD.
    Inventors: Sheng Wen Huang, Ai-Ke Huang, Jr-Je Chuang, Hsiao-Chun Hsu, Ya-Hsuan Lee
  • Patent number: 11874301
    Abstract: Probe systems including imaging devices with objective lens isolators and related methods are disclosed herein. A probe system includes an enclosure with an enclosure volume for enclosing a substrate that includes one or more devices under test (DUTs), a testing assembly, and an imaging device. The imaging device includes an imaging device objective lens, an imaging device body, and an objective lens isolator. In examples, the probe system includes an electrical grounding assembly configured to restrict electromagnetic noise from entering the enclosure volume. In examples, methods of preparing the imaging device include assembling the imaging device such that the imaging device objective lens is at least partially electrically isolated from the imaging device body. In some examples, utilizing the probe system includes testing the one or more DUTs while restricting electrical noise from propagating from the imaging device to the substrate.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: January 16, 2024
    Assignee: FormFactor, Inc.
    Inventors: Kazuki Negishi, Yu-Wen Huang, Gerald Lee Gisler, Eric Robert Christenson, Michael E. Simmons
  • Patent number: 11874166
    Abstract: The present application discloses a light sensor circuit, which comprises a photodiode and a capacitor unit. The cathode of the photodiode is controlled by a capacitive unit to maintain the same or close voltage level as the anode of the photodiode, which significantly reduces the effect of the dark current of the photodiode. Thus, the light sensor circuit can effectively maintain the performance and accuracy of an analog-to-digital converter applying the light sensor circuit. The circuit design difficulty and manufacturing cost are also significantly reduced.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: January 16, 2024
    Assignee: Sensortek Technology Corp.
    Inventors: Wen-Cheng Chen, Kai-Hsiang Chan, Sheng-Wen Huang
  • Publication number: 20240013001
    Abstract: A recognition method includes the following steps. A text is analyzed by a language recognition network to generate an entity feature, a relation feature and an overall feature. An input image is analyzed by an object detection network to generate candidate regions. Node features, aggregated edge features and compound features are generated by an enhanced cross-modal graph attention network according to the entity feature, the relation feature, the candidate regions and the overall feature. The entity feature and the relation feature are matched to the node features and the aggregated edge features to generate the first scores. The overall feature is matched to the compound features to generate second scores. Final scores corresponding to the candidate regions are generated according to the first scores and the second scores.
    Type: Application
    Filed: July 10, 2023
    Publication date: January 11, 2024
    Inventors: Jia WANG, Jing-Cheng KE, Wen-Huang CHENG, Hong-Han SHUAI, Yung-Hui LI
  • Patent number: 11858111
    Abstract: A foldable torque tool is provided, including a handle, a driving member and a blocking structure. The driving member is rotatably disposed on the handle. The blocking structure has a first blocking unit and a second blocking unit. The first blocking unit is disposed on the handle. The second blocking unit is disposed on the driving member. When the driving member is in an unfolded position, the first blocking unit is blocked with the second blocking unit, and then the driving member is non-rotatable to a folded position.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: January 2, 2024
    Inventor: Hung-Wen Huang
  • Patent number: 11856227
    Abstract: Video encoding methods and apparatuses in a video encoding system receive an input residual signal of a current block by a shared transform circuit, apply horizontal transform and vertical transform by a shared transform circuit to generate transform coefficients, apply quantization and inverse quantization to generate recovered transform coefficients, apply inverse vertical transform and inverse horizontal transform to the recovered transform coefficients by the shared transform circuit to generate a reconstructed residual signal for the current block, and encode the current block based on quantized levels of the current block. The shared transform circuit and a coefficient buffer in the folded 4-time transform architecture reuse computation resources in each transform stage. In some embodiments of the folded 4-time transform architecture, a hierarchical design for block size grouping is implemented with fixed throughput for uniform hardware scheduling.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: December 26, 2023
    Assignee: MEDIATEK INC.
    Inventors: Chih-Hsuan Lo, Man-Shu Chiang, Chun-Chia Chen, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang
  • Publication number: 20230404474
    Abstract: An evaluation method of sleep quality and a computing apparatus related to sleep quality are provided. In the evaluation method, sensing data is obtained. The sensing data is generated based on a radar echo. The sensing data is transformed into feature data. The feature data includes a statistic of a plurality of feature points on a waveform of the radar echo. Sleep quality information is determined according to the feature data. Accordingly, sleep quality may be evaluated through non-touch sensing.
    Type: Application
    Filed: March 27, 2023
    Publication date: December 21, 2023
    Applicants: Wistron Corporation, Taipei Medical University
    Inventors: Yu-Hsuan Ho, Yu-Wen Huang, Wen-Te Liu
  • Publication number: 20230409927
    Abstract: A data predicting method and apparatus are provided. In the method, distances between a predicting data and multiple data groups are determined. A first machine learning model corresponding the data group having the shortest distance with the predicting data is selected from multiple machine learning models. The predicting data is predicted through the first machine learning model. Those machine learning models are trained by using different data groups, respectively.
    Type: Application
    Filed: December 19, 2022
    Publication date: December 21, 2023
    Applicant: Wistron Corporation
    Inventors: Yu-Hsuan Ho, Yu-Wen Huang
  • Patent number: 11848297
    Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions spaced from the die mount portion; a semiconductor die over the die mount portion having bond pads on an active surface facing away from the package substrate; non-gold bond wires forming electrical connections between at least one of the bond pads and one of the lead portions of the package substrate; a bond stitch on bump connection formed between one of the non-gold bond wires and a bond pad of the semiconductor die, comprising a stitch bond formed on a flex stud bump; and dielectric material covering a portion of the package substrate, the semiconductor die, the non-gold bond wires, the stitch bond and the flex stud bump, forming a packaged semiconductor device.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: December 19, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Bo-Hsun Pan, Chien-Chang Li, Hung-Yu Chou, Shawn Martin O'Connor, Byron Lovell Williams, Jeffrey Alan West, Zi-Xian Zhan, Sheng-Wen Huang
  • Publication number: 20230402480
    Abstract: A method of manufacturing a semiconductor device includes disposing a plurality of a first type of light sensing units on a substrate; and disposing a plurality of a second type of light sensing units arranged on the substrate. Each of the first type of light sensing units is operable to receive less radiation than each of the second type of light sensing units. At least one of the second type of light sensing units is adjacent to a portion of at least one of the first type of light sensing units. The method includes disposing a first isolation structure between one of the first type of light sensing units and one of the second type of light sensing units; and disposing a second isolation structure between the adjacent first type of light sensing units. The method includes disposing a reflective layer above the first type of light sensing units.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 14, 2023
    Inventors: Li-Wen HUANG, Chung-Lin FANG, Kuan-Ling PAN, Ping-Hao LIN, Kuo-Cheng LEE, Cheng-Ming WU
  • Patent number: 11842703
    Abstract: The panel driving circuit includes a channel circuit, first pads, first switches, a second pad, and at least one second switch. The first pads are configured to be electrically connected to data lines of a cholesteric liquid crystal (CHLC) panel respectively. Each first switch has a first terminal electrically connected to the channel circuit, and a second terminal electrically connected to one of the first pads. Each second switch has a first terminal electrically connected to the second pad, and a second terminal electrically connected to the first pads. In a pixel charging period, the first switches are turned on, and the second switch is turned off. In a test period, the first switch is turned off, the second switch is turned on, and the second pad is configured to receive a measurement signal for measuring capacitance of pixels in the CHLC panel.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: December 12, 2023
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventor: Han Wen Huang
  • Publication number: 20230392878
    Abstract: An exposed tube cold plate structure includes a plate body and a water cooling tube. The plate body is formed with a groove. The water cooling tube is pressed and inlaid in the groove. The water cooling tube has a water cooling tube passage for a working medium to flow through. The water cooling tube passage has a passage inner wall. Multiple raised bodies and multiple channels are annularly alternately disposed on the passage inner wall for greatly enlarging the contact area between the passage inner wall and the working medium. In addition, the working medium flows through the water cooling tube passage in a state of turbulent flow so as to enhance the heat exchange amount of the cold plate.
    Type: Application
    Filed: February 22, 2023
    Publication date: December 7, 2023
    Inventors: Dan-Jun Chen, Guo-Hui Li, Chuan-Wen Huang
  • Patent number: 11836875
    Abstract: An augmented reality screen system includes an augmented reality device and a host. The augmented reality device is configured to take a physical mark through a camera. The host is configured to receive the physical mark, determine position information and rotation information of the physical mark, and fetch a virtual image from a storage device through a processor of the host. The processor transmits an adjusted virtual image to the augmented reality device according to the position information and the rotation information, and the augmentation device projects the adjusted virtual image to a display of the augmented reality device. The adjusted virtual image becomes a virtual extended screen, and the virtual extended screen and the physical mark are simultaneously displayed on the display of the augmented reality device.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: December 5, 2023
    Assignee: ACER INCORPORATED
    Inventors: Huei-Ping Tzeng, Chao-Kuang Yang, Wen-Cheng Hsu, Chih-Wen Huang, Chih-Haw Tan
  • Patent number: 11838557
    Abstract: Video encoding methods and apparatuses include receiving reconstructed video samples, determining an initial clipping setting for ALF coefficients, deriving clipping setting candidates from the initial clipping setting. ALF coefficients for the initial clipping setting and the clipping setting candidates are derived by solving inverse matrices, where partial intermediate results of solving ALF coefficients are shared by two or more clipping settings. A distortion value corresponds to the derived ALF coefficients for each clipping setting is computed, and final clipping indices for final ALF coefficients are determined according to the distortion values. ALF filtering is applied to the reconstructed video samples based on the final ALF coefficients and the final clipping indices.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: December 5, 2023
    Assignee: MEDIATEK INC.
    Inventors: Shih-Chun Chiu, Chih-Wei Hsu, Ching-Yeh Chen, Chun-Chia Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Patent number: 11832866
    Abstract: A system for performing ablation includes an ablation device (102) configured to ablate tissue in accordance with control parameters and configured to make measurements during the ablation process. An imaging system (104) is configured to measure an elastographic related parameter to monitor ablation progress. A parameter estimation and monitoring module (115) is configured to receive the measurements from the ablation device and/or the elastographic related parameter to provide feedback to adaptively adjust imaging parameters of the imaging device at different times during an ablation process.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: December 5, 2023
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Shyam Bharat, Ajay Anand, Shriram Sethuraman, Sheng-Wen Huang, William Tao Shi
  • Publication number: 20230383138
    Abstract: A manufacturing method of an elastic paint is provided. The manufacturing method includes: blending an original composition to produce a first rough painting material, where the original composition includes polycarbonatediol (PCDL), a polyurethane (PU) elastic powder, poly(methyl methacrylate) (PMMA), a photoinitiator, a wetting agent, a solvent, and an auxiliary agent; carrying out precipitation treatment on the first rough painting material, and filtering the treated first rough painting material, to produce a second rough painting material; blending the second rough painting material; sealing the blended second rough painting material to produce a plurality of layers in the second rough painting material; removing an upper portion and a lower portion from the layers to produce a main ingredient; and adding a curing agent and a diluent into the main ingredient to produce an elastic paint.
    Type: Application
    Filed: December 6, 2022
    Publication date: November 30, 2023
    Inventors: Guo Lin YANG, Po-Wen HUANG, Yu-Chun YANG
  • Publication number: 20230388546
    Abstract: Video encoding methods and apparatuses in a video encoding system receive an input residual signal of a current block by a shared transform circuit, apply horizontal transform and vertical transform by a shared transform circuit to generate transform coefficients, apply quantization and inverse quantization to generate recovered transform coefficients, apply inverse vertical transform and inverse horizontal transform to the recovered transform coefficients by the shared transform circuit to generate a reconstructed residual signal for the current block, and encode the current block based on quantized levels of the current block. The shared transform circuit and a coefficient buffer in the folded 4-time transform architecture reuse computation resources in each transform stage. In some embodiments of the folded 4-time transform architecture, a hierarchical design for block size grouping is implemented with fixed throughput for uniform hardware scheduling.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Inventors: Chih-Hsuan LO, Man-Shu CHIANG, Chun-Chia CHEN, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Patent number: 11832438
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: November 28, 2023
    Assignee: Intel Corporation
    Inventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Jared Stoeger, Yu-Wen Huang, Shu Zhou
  • Publication number: 20230378058
    Abstract: Semiconductor packages and methods of forming the same are disclosed. An semiconductor package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.
    Type: Application
    Filed: August 1, 2023
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Publication number: 20230369540
    Abstract: A semiconductor stack includes a first-type semiconductor layer, a second-type semiconductor layer, an active region located between the first-type semiconductor layer and the second-type semiconductor layer, one or multiple recesses, and a recess-induced layer located between the first-type semiconductor layer and the active region. The active region has a first thickness and includes an upper surface and a lower surface closer to the first-type semiconductor layer than the upper surface. Each recess includes a bottom disposed in the active region. A first distance is from the bottom of the recess to the lower surface. The first distance is 0.5-0.9 times the first thickness.
    Type: Application
    Filed: May 11, 2023
    Publication date: November 16, 2023
    Inventor: Feng-Wen HUANG